# `fabsx` — Floating Absolute Value

> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc000210`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `fabs` | `fabsx` | — | Floating Absolute Value |
| `fabs.` | `fabsx` | Rc=1 | Floating Absolute Value |

## Syntax

```asm
fabs[Rc] [FD], [FB]
```

## Encoding

### `fabsx` — form `X`

- **Opcode word:** `0xfc000210`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `264`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FB` | fabsx: read | Source B floating-point register. |
| `FD` | fabsx: write | Destination floating-point register. |
| `CR` | fabsx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |

## Register Effects

### `fabsx`

- **Reads (always):** `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FD`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `fabsx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.

## Operation (pseudocode)

```
FRT <- clear_sign(FRB)
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`fabsx`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fabsx"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:478`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L478)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:27`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L27)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:909`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L909)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2757-2761`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2757-L2761)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::fabsx => {
            ctx.fpr[instr.rd()] = ctx.fpr[instr.rb()].abs();
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Bit-pattern operation, no rounding.** `fabs` clears the sign bit (bit 0) of the source FPR's binary64 representation and writes the 64-bit value to the destination unchanged otherwise. No precision loss, no FPSCR exception bits. The mnemonic does not have an `s` variant — there is one form regardless of whether the operand is interpreted as binary32 or binary64.
- **NaN handling.** `fabs(NaN)` returns the same NaN with the sign bit cleared. The signalling/quiet bit is **not** modified, and `FPSCR[VXSNAN]` is **not** raised. xenia-rs uses `f64::abs`, which matches: it is bit-level `x & 0x7FFF_FFFF_FFFF_FFFF`.
- **Special values.** `fabs(±0) = +0`; `fabs(±∞) = +∞`; `fabs(±NaN)` = `+NaN` (sign cleared, payload preserved).
- **FPSCR is largely untouched.** Hardware specifies `FPRF` is **not** updated by `fabs`, and no exception bits are raised. Notation in the page header about `FPSCR` write is generic — the only meaningful write is via `Rc=1`.
- **`Rc=1` (`fabs.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1 (these bits are typically stale or zero).
- **No `FRA` operand.** X-form, primary 63, XO 264. Reads `FRB` only; bits 11–15 are don't-care.
- **Common idiom.** `fabs` followed by `fcmpu` against a small constant for ULP-sized "near zero" tests; or paired with `fneg`/`fnabs` for sign-set-to-known operations.

## Related Instructions

- [`fnegx`](fnegx.md) — flip sign bit.
- [`fnabsx`](fnabsx.md) — absolute value with sign **set** (always negative result).
- [`fmrx`](fmrx.md) — copy FPR (no sign manipulation).
- [`fselx`](fselx.md) — branch-free select; combined with `fabs` for `min`/`max`/`clamp` patterns.
- [`fcmpux`](fcmpu.md), [`fcmpox`](fcmpo.md) — compares often paired with `fabs` for magnitude tests.

## IBM Reference

- [AIX 7.3 — `fabs` (Floating Absolute Value)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fabs-floating-absolute-value-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/) (sign-bit manipulation defined as bit-pattern, not arithmetic).