# `fctidzx` — Floating Convert to Integer Doubleword with Round Toward Zero

> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc00065e`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `fctidz` | `fctidzx` | — | Floating Convert to Integer Doubleword with Round Toward Zero |
| `fctidz.` | `fctidzx` | Rc=1 | Floating Convert to Integer Doubleword with Round Toward Zero |

## Syntax

```asm
fctidz[Rc] [FD], [FB]
```

## Encoding

### `fctidzx` — form `X`

- **Opcode word:** `0xfc00065e`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `815`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FB` | fctidzx: read | Source B floating-point register. |
| `FD` | fctidzx: write | Destination floating-point register. |
| `CR` | fctidzx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
| `FPSCR` | fctidzx: write | Floating-Point Status and Control Register. |

## Register Effects

### `fctidzx`

- **Reads (always):** `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FD`, `FPSCR`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `fctidzx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`fctidzx`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fctidzx"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:285`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L285)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:27`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L27)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:913`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L913)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2907-2927`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2907-L2927)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::fctidzx => {
            // Convert to integer doubleword (round toward zero).
            // PPCBUG-229: set XX on inexact.
            let val = ctx.fpr[instr.rb()];
            let result = if val.is_nan() {
                fpscr::set_exception(ctx, fpscr::VXCVI | if fpscr::is_snan(val) { fpscr::VXSNAN } else { 0 });
                0x8000_0000_0000_0000u64
            } else if val >= (i64::MAX as f64) {
                fpscr::set_exception(ctx, fpscr::VXCVI);
                0x7FFF_FFFF_FFFF_FFFFu64
            } else if val < (i64::MIN as f64) {
                fpscr::set_exception(ctx, fpscr::VXCVI);
                0x8000_0000_0000_0000u64
            } else {
                if val != val.trunc() { fpscr::set_exception(ctx, fpscr::XX); }
                (val.trunc() as i64) as u64
            };
            ctx.fpr[instr.rd()] = f64::from_bits(result);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **binary64 → 64-bit signed integer, round toward zero.** The "z" suffix forces truncation regardless of `FPSCR[RN]`. xenia-rs uses Rust's `as i64` (which truncates toward zero), bypassing the FPSCR rounding mode entirely — this matches PPC `fctidz` semantics correctly.
- **Saturation on out-of-range.** PowerISA: out-of-range or NaN → `0x8000_0000_0000_0000` and `FPSCR[VXCVI, VX, FX]`. xenia handles NaN explicitly with the sentinel, but uses raw `as i64` for finite values; in current Rust (since 1.45) `as i64` from out-of-range `f64` is **defined to saturate** to `i64::MIN`/`i64::MAX`. So:
  - **+∞ or large positive → `i64::MAX`** (`0x7FFF_FFFF_FFFF_FFFF`) under xenia.
  - **−∞ or large negative → `i64::MIN`** (`0x8000_0000_0000_0000`) under xenia.
  - **PPC** spec returns `0x8000_0000_0000_0000` for both. **xenia quirk:** positive overflow returns the wrong sentinel.
- **NaN.** Returns sentinel `0x8000_0000_0000_0000` (matches PPC).
- **Inexact.** Sets `FPSCR[XX, FX]` on any non-integer input. xenia does not update FPSCR (xenia quirk).
- **No `FPSCR[RN]` dependence.** `fctidz` always truncates; this is the right choice for C/C++ `(int64_t)` casts.
- **`Rc=1` (`fctidz.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
- **Encoding.** X-form, primary 63, XO 815. Reads `FRB` only.
- **Common pairing.** Translation of C `(int64_t)d` casts; combined with `stfd` to move the value to integer memory.

## Related Instructions

- [`fctidx`](fctidx.md) — same conversion but uses `FPSCR[RN]` (default nearest-even on PPC; xenia uses `f64::round` regardless).
- [`fctiwzx`](fctiwzx.md) — 32-bit truncating variant.
- [`fctiwx`](fctiwx.md) — 32-bit `FPSCR[RN]`-rounded variant.
- [`fcfidx`](fcfidx.md) — inverse direction.
- `stfd` — store the integer-bits FPR to memory.

## IBM Reference

- [AIX 7.3 — `fctidz` (Floating Convert to Integer Doubleword with Round Toward Zero)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fctidz-floating-convert-integer-doubleword-round-toward-zero-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/).