# `ld` — Load Doubleword
> **Category:** [Memory](../categories/memory.md) · **Form:** [DS](../forms/DS.md) · **Opcode:** `0xe8000000`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `ld` | `ld` | — | Load Doubleword |
| `ldu` | `ldu` | — | Load Doubleword with Update |
| `ldux` | `ldux` | — | Load Doubleword with Update Indexed |
| `ldx` | `ldx` | — | Load Doubleword Indexed |
## Syntax
```asm
ld [RD], [ds]([RA0])
ldu [RD], [ds]([RA])
ldux [RD], [RA], [RB]
ldx [RD], [RA0], [RB]
```
## Encoding
### `ld` — form `DS`
- **Opcode word:** `0xe8000000`
- **Primary opcode (bits 0–5):** `58`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
| 16–29 | `DS` | 14-bit signed word-scaled displacement |
| 30–31 | `XO` | extended opcode |
### `ldu` — form `DS`
- **Opcode word:** `0xe8000001`
- **Primary opcode (bits 0–5):** `58`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
| 16–29 | `DS` | 14-bit signed word-scaled displacement |
| 30–31 | `XO` | extended opcode |
### `ldux` — form `X`
- **Opcode word:** `0x7c00006a`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `53`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `ldx` — form `X`
- **Opcode word:** `0x7c00002a`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `21`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `RA0` | ld: read; ldx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `ds` | ld: read; ldu: read | 14-bit signed word-aligned displacement (`DS << 2`). |
| `RD` | ld: write; ldu: write; ldux: write; ldx: write | Destination GPR. |
| `RA` | ldu: read; ldu: write; ldux: read; ldux: write | Source GPR (`r0`–`r31`). |
| `RB` | ldux: read; ldx: read | Source GPR. |
## Register Effects
### `ld`
- **Reads (always):** `RA0`, `ds`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** _none_
### `ldu`
- **Reads (always):** `RA`, `ds`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`, `RA`
- **Writes (conditional):** _none_
### `ldux`
- **Reads (always):** `RA`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`, `RA`
- **Writes (conditional):** _none_
### `ldx`
- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
EA <- (RA|0) + EXTS(ds || 0b00)
RT <- MEM(EA, 8)
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`ld`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="ld"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:347`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L347)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:36`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L36)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:380`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L380)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1096-1101`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1096-L1101)
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::ld => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = ea.wrapping_add(instr.ds() as i64 as u64) as u32;
ctx.gpr[instr.rd()] = mem.read_u64(ea);
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::ldu => {
let ea = ctx.gpr[instr.ra()].wrapping_add(instr.ds() as i64 as u64) as u32;
ctx.gpr[instr.rd()] = mem.read_u64(ea);
ctx.gpr[instr.ra()] = ea as u64;
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::ldux => {
let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
ctx.gpr[instr.rd()] = mem.read_u64(ea);
ctx.gpr[instr.ra()] = ea as u64;
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::ldx => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
ctx.gpr[instr.rd()] = mem.read_u64(ea);
ctx.pc += 4;
}
```