# `lwz` — Load Word and Zero
> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x80000000`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `lwz` | `lwz` | — | Load Word and Zero |
| `lwzu` | `lwzu` | — | Load Word and Zero with Update |
| `lwzux` | `lwzux` | — | Load Word and Zero with Update Indexed |
| `lwzx` | `lwzx` | — | Load Word and Zero Indexed |
## Syntax
```asm
lwz [RD], [d]([RA0])
lwzu [RD], [d]([RA])
lwzux [RD], [RA], [RB]
lwzx [RD], [RA0], [RB]
```
## Encoding
### `lwz` — form `D`
- **Opcode word:** `0x80000000`
- **Primary opcode (bits 0–5):** `32`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
### `lwzu` — form `D`
- **Opcode word:** `0x84000000`
- **Primary opcode (bits 0–5):** `33`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
### `lwzux` — form `X`
- **Opcode word:** `0x7c00006e`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `55`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `lwzx` — form `X`
- **Opcode word:** `0x7c00002e`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `23`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `RA0` | lwz: read; lwzx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `d` | lwz: read; lwzu: read | 16-bit signed displacement (`d`) added to the base address register. |
| `RD` | lwz: write; lwzu: write; lwzux: write; lwzx: write | Destination GPR. |
| `RA` | lwzu: read; lwzu: write; lwzux: read; lwzux: write | Source GPR (`r0`–`r31`). |
| `RB` | lwzux: read; lwzx: read | Source GPR. |
## Register Effects
### `lwz`
- **Reads (always):** `RA0`, `d`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** _none_
### `lwzu`
- **Reads (always):** `RA`, `d`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`, `RA`
- **Writes (conditional):** _none_
### `lwzux`
- **Reads (always):** `RA`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`, `RA`
- **Writes (conditional):** _none_
### `lwzx`
- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
EA <- (RA|0) + EXTS(d)
RT <- ZEXT32_to_64(MEM(EA, 4))
```
## C Translation Example
```c
/* lwz RT, d(RA) */
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
uint32_t ea = (uint32_t)(base + (int64_t)(int16_t)insn.D);
r[insn.RT] = (uint64_t)mem_read_u32_be(ea); /* zero-extend */
```
## Implementation References
**`lwz`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lwz"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:289`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L289)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:49`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L49)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:355`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L355)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1000-1005`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1000-L1005)
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::lwz => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = ea.wrapping_add(instr.d() as i64 as u64) as u32;
ctx.gpr[instr.rd()] = mem.read_u32(ea) as u64;
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::lwzu => {
let ea = ctx.gpr[instr.ra()].wrapping_add(instr.d() as i64 as u64) as u32;
ctx.gpr[instr.rd()] = mem.read_u32(ea) as u64;
ctx.gpr[instr.ra()] = ea as u64;
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::lwzux => {
let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
ctx.gpr[instr.rd()] = mem.read_u32(ea) as u64;
ctx.gpr[instr.ra()] = ea as u64;
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::lwzx => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
ctx.gpr[instr.rd()] = mem.read_u32(ea) as u64;
ctx.pc += 4;
}
```