# `vcmpgefp` — Vector Compare Greater-Than-or-Equal-to Floating Point
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VC](../forms/VC.md) · **Opcode:** `0x100001c6`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vcmpgefp` | `vcmpgefp` | — | Vector Compare Greater-Than-or-Equal-to Floating Point |
| `vcmpgefp.` | `vcmpgefp` | Rc=1 | Vector Compare Greater-Than-or-Equal-to Floating Point |
| `vcmpgefp128` | `vcmpgefp128` | — | Vector128 Compare Greater-Than-or-Equal-to Floating Point |
| `vcmpgefp128.` | `vcmpgefp128` | Rc=1 | Vector128 Compare Greater-Than-or-Equal-to Floating Point |
## Syntax
```asm
vcmpgefp[Rc] [VD], [VA], [VB]
vcmpgefp128[Rc] [VD], [VA], [VB]
```
## Encoding
### `vcmpgefp` — form `VC`
- **Opcode word:** `0x100001c6`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `454`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21 | `Rc` | record-form flag (updates CR6) |
| 22–31 | `XO` | extended opcode (10 bits) |
### `vcmpgefp128` — form `VX128_R`
- **Opcode word:** `0x18000080`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `128`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22–25 | `XO` | extended opcode (compare) |
| 26 | `VA128h` | source A middle bit |
| 27 | `Rc` | record-form flag (updates CR6) |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VA` | vcmpgefp: read; vcmpgefp128: read | Source A vector register. |
| `VB` | vcmpgefp: read; vcmpgefp128: read | Source B vector register. |
| `VD` | vcmpgefp: write; vcmpgefp128: write | Destination vector register. |
| `CR` | vcmpgefp: write (conditional); vcmpgefp128: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
## Register Effects
### `vcmpgefp`
- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** `CR`
### `vcmpgefp128`
- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** `CR`
## Status-Register Effects
- `vcmpgefp`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.
- `vcmpgefp128`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.
## Operation (pseudocode)
```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vcmpgefp`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcmpgefp"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:631`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L631)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:96`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L96)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:561`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L561)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2184-2194`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2184-L2194)
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::vcmpgefp | PpcOpcode::vcmpgefp128 => {
let (va, vb, vd) = vmx_reg_triple(instr);
let a = ctx.vr[va].as_f32x4();
let b = ctx.vr[vb].as_f32x4();
let mut r = [0u32; 4];
for i in 0..4 { r[i] = if a[i] >= b[i] { 0xFFFF_FFFF } else { 0 }; }
ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
let rc = if matches!(instr.opcode, PpcOpcode::vcmpgefp128) { instr.vx128r_rc_bit() } else { instr.vc_rc_bit() };
if rc { update_cr6_from_vmask(&r, ctx); }
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::vcmpgefp | PpcOpcode::vcmpgefp128 => {
let (va, vb, vd) = vmx_reg_triple(instr);
let a = ctx.vr[va].as_f32x4();
let b = ctx.vr[vb].as_f32x4();
let mut r = [0u32; 4];
for i in 0..4 { r[i] = if a[i] >= b[i] { 0xFFFF_FFFF } else { 0 }; }
ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
let rc = if matches!(instr.opcode, PpcOpcode::vcmpgefp128) { instr.vx128r_rc_bit() } else { instr.vc_rc_bit() };
if rc { update_cr6_from_vmask(&r, ctx); }
ctx.pc += 4;
}
```