# `vmsummbm` — Vector Multiply-Sum Mixed-Sign Byte Modulo

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x10000025`

<!-- GENERATED: BEGIN -->

## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmsummbm` | `vmsummbm` | — | Vector Multiply-Sum Mixed-Sign Byte Modulo |

## Syntax

```asm
vmsummbm [VD], [VA], [VB], [VC]
```

## Encoding

### `vmsummbm` — form `VA`

- **Opcode word:** `0x10000025`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `37`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21–25 | `VRC` | source C / shift |
| 26–31 | `XO` | extended opcode (6 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmsummbm: read | Source A vector register. |
| `VB` | vmsummbm: read | Source B vector register. |
| `VC` | vmsummbm: read | Source C vector register / 3-bit selector. |
| `VD` | vmsummbm: write | Destination vector register. |

## Register Effects

### `vmsummbm`

- **Reads (always):** `VA`, `VB`, `VC`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vmsummbm`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmsummbm"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1037`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1037)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:107`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L107)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:580`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L580)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3579-3594`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3579-L3594)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vmsummbm => {
            // signed bytes × unsigned bytes, signed accumulator
            let a = crate::vmx::as_i8x16(ctx.vr[instr.ra()]);
            let b = ctx.vr[instr.rb()].as_bytes();
            let c = crate::vmx::as_i32x4(ctx.vr[instr.rc()]);
            let mut r = [0i32; 4];
            for i in 0..4 {
                let mut s = c[i];
                for j in 0..4 {
                    s = s.wrapping_add(a[4*i+j] as i32 * b[4*i+j] as i32);
                }
                r[i] = s;
            }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }
```
</details>

<!-- GENERATED: END -->

## Special Cases & Edge Conditions

- **Mixed signed×unsigned multiply-sum, modulo.** The "m" / "b" / "m" of `vmsummbm` decode as: `m`=mixed (signed `VA` × unsigned `VB`), `b`=byte lanes, `m`=modulo accumulator. Per word lane:
  ```
  VD[i] = (VC[i] + Σ_{j=0..3} int8(VA[4*i + j]) * uint8(VB[4*i + j])) mod 2^32
  ```
  Four signed-byte × unsigned-byte products are summed with a signed-word accumulator from `VC`, into a single signed word.
- **Mixed signedness is unique to this instruction** — it's the canonical "signed pixel weight × unsigned pixel value" combo for filter convolution.
- **No `VSCR[SAT]` change.** Modulo wrap; the saturating sibling for byte lanes does not exist (Altivec only provides a saturating `vmsum` for half-word widths).
- **Big-endian byte lanes.** Lane 0 is the most-significant byte; the four contributing bytes for output word `i` are bytes `4*i .. 4*i+3`.
- **No XER, no exceptions.**
- **Aliasing legal.**
- **No VMX128 sibling.**
- **Common usage.** Per-tile signed-weight pixel sums; H.264-style 4-tap signed filter on byte data.

## Related Instructions

- [`vmsumubm`](vmsumubm.md) — same shape, both sources unsigned (no signed weights).
- [`vmsumshm`](vmsumshm.md) / [`vmsumshs`](vmsumshs.md) — half-word × half-word multiply-sum (modulo / saturate).
- [`vmsumuhm`](vmsumuhm.md) / [`vmsumuhs`](vmsumuhs.md) — unsigned half-word multiply-sum.
- [`vmladduhm`](vmladduhm.md) — per-lane multiply-add at half width (no horizontal reduction).
- [`vsumsws`](vsumsws.md), [`vsum4sbs`](vsum4sbs.md) — pure horizontal sums.

## IBM Reference

- [AIX 7.3 — `vmsummbm` (Vector Multiply-Sum Mixed-Sign Byte Modulo)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmsummbm-vector-multiply-sum-mixed-sign-byte-modulo-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Sum Family](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)