# `vmulosh` — Vector Multiply Odd Signed Half Word

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000148`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmulosh` | `vmulosh` | — | Vector Multiply Odd Signed Half Word |

## Syntax

```asm
vmulosh [VD], [VA], [VB]
```

## Encoding

### `vmulosh` — form `VX`

- **Opcode word:** `0x10000148`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `328`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmulosh: read | Source A vector register. |
| `VB` | vmulosh: read | Source B vector register. |
| `VD` | vmulosh: write | Destination vector register. |

## Register Effects

### `vmulosh`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vmulosh`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmulosh"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1111`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1111)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:109`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L109)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:462`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L462)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3509-3516`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3509-L3516)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vmulosh => {
            let a = crate::vmx::as_i16x8(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i16x8(ctx.vr[instr.rb()]);
            let mut r = [0i32; 4];
            for i in 0..4 { r[i] = a[2 * i + 1] as i32 * b[2 * i + 1] as i32; }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Odd-lane signed half-word multiply.** Only half-word lanes 1, 3, 5, 7 of `VA` and `VB` (big-endian numbering) participate. Each pair is treated as signed 16-bit, multiplied, and sign-extended to a signed 32-bit word in `VD`. Pairing: `VD.w[i] = (int16)VA.h[2*i+1] * (int16)VB.h[2*i+1]` for `i ∈ 0..3`.
- **Lane-count reduction.** 8 half-word lanes → 4 word lanes.
- **No overflow.** `(-32768)*(-32768) = 0x40000000` — fits in int32. `VSCR[SAT]` is untouched.
- **Pair with [`vmulesh`](vmulesh.md)** for all eight products, then interleave with `vmrghw`/`vmrglw`. Feed into [`vmsumshm`](vmsumshm.md)/[`vmsumshs`](vmsumshs.md) for accumulation.
- **Signed arithmetic.** Negative inputs sign-extend before multiplication; contrast with [`vmulouh`](vmulouh.md).
- **No `Rc`, no XER.** No VMX128 sibling.

## Related Instructions

- [`vmulesh`](vmulesh.md) — even-lane signed half-word multiply.
- [`vmulouh`](vmulouh.md), [`vmuleuh`](vmuleuh.md) — unsigned half-word twins.
- [`vmulosb`](vmulosb.md), [`vmulesb`](vmulesb.md) — signed byte even/odd.
- [`vmhaddshs`](vmhaddshs.md), [`vmhraddshs`](vmhraddshs.md) — fused half-word fixed-point MAC variants.
- [`vmsumshm`](vmsumshm.md), [`vmsumshs`](vmsumshs.md) — signed multiply-sum modulo / saturating.

## IBM Reference

- [AIX 7.3 — `vmulosh` (Vector Multiply Odd Signed Half Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmulosh-vector-multiply-odd-signed-half-word-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)