# `vspltb` — Vector Splat Byte

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000020c`

<!-- GENERATED: BEGIN -->

## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vspltb` | `vspltb` | — | Vector Splat Byte |

## Syntax

```asm
vspltb [VD], [VB], [UIMM]
```

## Encoding

### `vspltb` — form `VX`

- **Opcode word:** `0x1000020c`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `524`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VB` | vspltb: read | Source B vector register. |
| `UIMM` | vspltb: read | 16-bit unsigned immediate. Zero-extended. |
| `VD` | vspltb: write | Destination vector register. |

## Register Effects

### `vspltb`

- **Reads (always):** `VB`, `UIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vspltb`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vspltb"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1503`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1503)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:123`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L123)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:480`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L480)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2349-2355`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2349-L2355)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vspltb => {
            let uimm = ((instr.raw >> 16) & 0xF) as usize;
            let b = ctx.vr[instr.rb()].as_bytes();
            let val = b[uimm];
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes([val; 16]);
            ctx.pc += 4;
        }
```
</details>

<!-- GENERATED: END -->

## Special Cases & Edge Conditions

- **Splat one byte across all 16 lanes.** The `UIMM` field (bits 11–15) selects which byte of `VB` to replicate — `UIMM = 0` picks the MSB lane, `UIMM = 15` picks the LSB. Only the low 4 bits are meaningful.
- **Big-endian index.** `UIMM = 0` → `VB.b[0]`, the most significant byte. This matches the layout after a `stvx` / `lvx` round-trip.
- **Typical use: broadcast a comparison selector or a shift count** so that a per-lane op (e.g. [`vslb`](vslb.md)) behaves as a scalar-style shift.
- **No flags, no VSCR.**
- **No VMX128 sibling.** Xenon replaces this with [`vspltisb`](vspltisb.md) for immediate constants, or with [`vpermwi128`](../vmx128/vpermwi128.md) / [`vperm`](vperm.md) for more complex splats.

## Related Instructions

- [`vsplth`](vsplth.md), [`vspltw`](vspltw.md) — half-word / word splat siblings.
- [`vspltisb`](vspltisb.md), [`vspltish`](vspltish.md), [`vspltisw`](vspltisw.md) — immediate splats (no source register needed).
- [`vperm`](vperm.md) — programmable byte permute; a splat is the special case where `VC = {k, k, …, k}`.
- [`vpermwi128`](../vmx128/vpermwi128.md) — word-level 4-way permute via 8-bit immediate (VMX128-only).

## IBM Reference

- [AIX 7.3 — `vspltb` (Vector Splat Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vspltb-vector-splat-byte-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)