# `vsplth` — Vector Splat Half Word

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000024c`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vsplth` | `vsplth` | — | Vector Splat Half Word |

## Syntax

```asm
vsplth [VD], [VB], [UIMM]
```

## Encoding

### `vsplth` — form `VX`

- **Opcode word:** `0x1000024c`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `588`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VB` | vsplth: read | Source B vector register. |
| `UIMM` | vsplth: read | 16-bit unsigned immediate. Zero-extended. |
| `VD` | vsplth: write | Destination vector register. |

## Register Effects

### `vsplth`

- **Reads (always):** `VB`, `UIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vsplth`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsplth"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1513`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1513)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:123`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L123)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:487`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L487)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2342-2348`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2342-L2348)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vsplth => {
            let uimm = ((instr.raw >> 16) & 0x7) as usize;
            let b = ctx.vr[instr.rb()].as_u16x8();
            let val = b[uimm];
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array([val; 8]);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Splat one half-word across all 8 lanes.** `UIMM` (bits 11–15, low 3 bits honoured) selects which of `VB`'s 8 half-word lanes is replicated.
- **Big-endian index.** `UIMM = 0` → `VB.h[0]`, the most significant half-word.
- **Typical use: broadcast a 16-bit shift count or comparison operand.**
- **No flags, no VSCR.**
- **No VMX128 sibling.**

## Related Instructions

- [`vspltb`](vspltb.md), [`vspltw`](vspltw.md) — byte / word splat siblings.
- [`vspltish`](vspltish.md) — immediate-operand splat (no source register).
- [`vperm`](vperm.md) — programmable permute; a half-word splat maps to a per-byte selector of `{2k, 2k+1, 2k, 2k+1, …}`.
- [`vpermwi128`](../vmx128/vpermwi128.md) — word-level permute (VMX128-only).

## IBM Reference

- [AIX 7.3 — `vsplth` (Vector Splat Half Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsplth-vector-splat-half-word-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)