# `vsrab` — Vector Shift Right Algebraic Byte

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000304`

<!-- GENERATED: BEGIN -->

## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vsrab` | `vsrab` | — | Vector Shift Right Algebraic Byte |

## Syntax

```asm
vsrab [VD], [VA], [VB]
```

## Encoding

### `vsrab` — form `VX`

- **Opcode word:** `0x10000304`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `772`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vsrab: read | Source A vector register. |
| `VB` | vsrab: read | Source B vector register. |
| `VD` | vsrab: write | Destination vector register. |

## Register Effects

### `vsrab`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vsrab`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsrab"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1599`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1599)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:124`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L124)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:500`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L500)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3868-3875`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3868-L3875)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vsrab => {
            let a = crate::vmx::as_i8x16(ctx.vr[instr.ra()]);
            let b = ctx.vr[instr.rb()].as_bytes();
            let mut r = [0i8; 16];
            for i in 0..16 { r[i] = a[i] >> (b[i] & 7); }
            ctx.vr[instr.rd()] = crate::vmx::from_i8x16(r);
            ctx.pc += 4;
        }
```
</details>

<!-- GENERATED: END -->

## Special Cases & Edge Conditions

- **Per-lane arithmetic right-shift of signed bytes.** `VD.b[i] = (int8)VA.b[i] >> (VB.b[i] & 7)` — sign bit propagates into vacated high-order bits. Low 3 bits of each shift-count byte are honoured.
- **Per-lane shift counts.** Splat via [`vspltb`](vspltb.md) / [`vspltisb`](vspltisb.md) for uniform shifts.
- **Sign extension.** Negative inputs produce values that stay negative (toward `-1`), unlike logical shift [`vsrb`](vsrb.md) which zero-fills.
- **Big-endian byte lanes.**
- **No flags, no VSCR.**
- **No VMX128 sibling.**

## Related Instructions

- [`vsrb`](vsrb.md) — logical-right byte shift.
- [`vslb`](vslb.md) — byte logical-left.
- [`vrlb`](vrlb.md) — byte rotate.
- [`vsrah`](vsrah.md), [`vsraw`](vsraw.md) — arithmetic-right half-word / word.

## IBM Reference

- [AIX 7.3 — `vsrab` (Vector Shift Right Arithmetic Integer Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsrab-vector-shift-right-algebraic-integer-byte-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)