# `vsum4shs` — Vector Sum Across Partial (1/4) Signed Half Word Saturate

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000648`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vsum4shs` | `vsum4shs` | — | Vector Sum Across Partial (1/4) Signed Half Word Saturate |

## Syntax

```asm
vsum4shs [VD], [VA], [VB]
```

## Encoding

### `vsum4shs` — form `VX`

- **Opcode word:** `0x10000648`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `1608`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vsum4shs: read | Source A vector register. |
| `VB` | vsum4shs: read | Source B vector register. |
| `VD` | vsum4shs: write | Destination vector register. |
| `VSCR` | vsum4shs: write | Vector Status and Control Register (NJ/SAT bits). |

## Register Effects

### `vsum4shs`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`, `VSCR`
- **Writes (conditional):** _none_

## Status-Register Effects

- `vsum4shs`: **VSCR[SAT]** may be stickied on saturating vector operations.

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vsum4shs`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsum4shs"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1786`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1786)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:127`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L127)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:543`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L543)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3706-3718`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3706-L3718)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vsum4shs => {
            let a = crate::vmx::as_i16x8(ctx.vr[instr.ra()]);
            let c = crate::vmx::as_i32x4(ctx.vr[instr.rb()]);
            let mut r = [0i32; 4]; let mut sat = false;
            for i in 0..4 {
                let s = a[2*i] as i64 + a[2*i+1] as i64 + c[i] as i64;
                let (v, o) = crate::vmx::sat_i64_to_i32(s);
                r[i] = v; sat |= o;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Per-word 2-half-word partial sum (signed).** For each of the 4 output word lanes, sum 2 signed half-words of `VA` plus the matching signed word of `VB`, then saturate to `int32`. `VD.w[i] = sat(VA.h[2*i] + VA.h[2*i+1] + VB.w[i])`.
- **Sticky VSCR[SAT]** set on overflow.
- **Useful bridge between 16-bit multiply results and 32-bit accumulators.** Often pairs with `vmulesh` / `vmulosh`.
- **Big-endian half-word / word lanes.**
- **No `Rc`, no XER.**
- **No VMX128 sibling.**

## Related Instructions

- [`vsum4sbs`](vsum4sbs.md) — signed byte variant.
- [`vsum4ubs`](vsum4ubs.md) — unsigned byte variant.
- [`vsum2sws`](vsum2sws.md), [`vsumsws`](vsumsws.md) — wider reductions.
- [`vmhaddshs`](vmhaddshs.md), [`vmsumshm`](vmsumshm.md), [`vmsumshs`](vmsumshs.md) — fused multiply-sum cousins.

## IBM Reference

- [AIX 7.3 — `vsum4shs` (Vector Sum across Partial (1/4) Saturated Signed Half Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsum4shs-vector-sum-across-partial-14-saturated-signed-half-word-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)