# `vupklpx` — Vector Unpack Low Pixel > **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x100003ce` ## Assembler Mnemonics | Mnemonic | XML entry | Flags | Description | | --- | --- | --- | --- | | `vupklp` | `vupklpx` | — | Vector Unpack Low Pixel | ## Syntax ```asm vupklpx [VD], [VB] ``` ## Encoding ### `vupklpx` — form `VX` - **Opcode word:** `0x100003ce` - **Primary opcode (bits 0–5):** `4` - **Extended opcode:** `974` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode (4) | | 6–10 | `VRT/VD` | destination vector register | | 11–15 | `VRA/VA` | source A vector register | | 16–20 | `VRB/VB` | source B vector register | | 21–31 | `XO` | extended opcode (11 bits) | ## Operands | Field | Role | Description | | --- | --- | --- | | `VB` | vupklpx: read | Source B vector register. | | `VD` | vupklpx: write | Destination vector register. | ## Register Effects ### `vupklpx` - **Reads (always):** `VB` - **Reads (conditional):** _none_ - **Writes (always):** `VD` - **Writes (conditional):** _none_ ## Status-Register Effects _No condition-register or status-register effects._ ## Operation (pseudocode) ``` ; Pseudocode derives directly from the xenia-rs interpreter ; arm (see Implementation References). Operation semantics: ; - Read source operands from the fields listed under Operands. ; - Apply the arithmetic / logical / memory action described ; in the Description field above. ; - Write results to the destination register(s); update any ; status bits enumerated under Status-Register Effects. ; Consult the IBM AIX reference link under IBM Reference for ; canonical PPC-style pseudocode where xenia's expression is ; terse. ``` ## C Translation Example ```c /* C translation: the xenia-rs interpreter arm below in */ /* Implementation References is the authoritative semantic */ /* snapshot. Translate it line-by-line: */ /* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */ /* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */ /* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */ /* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */ /* The Register Effects and Status-Register Effects tables above */ /* enumerate every side effect a faithful translation must emit. */ ``` ## Implementation References **`vupklpx`** - xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vupklpx"`](../../xenia-canary/tools/ppc-instructions.xml) - xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:2007`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L2007) - xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:129`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L129) - xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:518`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L518) - xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4175-4181`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4175-L4181)
xenia-rs interpreter body (frozen snapshot) ```rust PpcOpcode::vupklpx => { let b = ctx.vr[instr.rb()].as_u16x8(); let mut r = [0u32; 4]; for i in 0..4 { r[i] = crate::vmx::unpack_pixel_555(b[4 + i]); } ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r); ctx.pc += 4; } ```
## Special Cases & Edge Conditions - **Unpack the low 4 of 8 pixel half-words.** The lower half-words of `VB` (`VB.h[4..7]`) are each decoded from 1-5-5-5 pixel format into a 32-bit word (`1.5.5.5 → 1.8.8.8`). Xenia uses `vmx::unpack_pixel_555`. - **Output layout.** `VD.w[0..3]` receive the 4 decoded pixels in big-endian order. - **Inverse of the low half of [`vpkpx`](vpkpx.md).** - **No saturation, no flags, no VSCR.** - **No VMX128 sibling.** VMX128 uses [`vupkd3d128`](../vmx128/vupkd3d128.md) for richer formats. ## Related Instructions - [`vupkhpx`](vupkhpx.md) — high-half pixel unpack. - [`vpkpx`](vpkpx.md) — the inverse pack. - [`vupkhsb`](vupkhsb.md), [`vupklsb`](vupklsb.md), [`vupkhsh`](vupkhsh.md), [`vupklsh`](vupklsh.md) — sign-extending unpacks. - [`vupkd3d128`](../vmx128/vupkd3d128.md) — VMX128 D3D-format unpack. ## IBM Reference - [AIX 7.3 — `vupklpx` (Vector Unpack Low Pixel16)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vupklpx-vector-unpack-low-pixel16-instruction) - [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)