# `vupklsh` — Vector Unpack Low Signed Half Word

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x100002ce`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vupklsh` | `vupklsh` | — | Vector Unpack Low Signed Half Word |

## Syntax

```asm
vupklsh [VD], [VB]
```

## Encoding

### `vupklsh` — form `VX`

- **Opcode word:** `0x100002ce`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `718`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VB` | vupklsh: read | Source B vector register. |
| `VD` | vupklsh: write | Destination vector register. |

## Register Effects

### `vupklsh`

- **Reads (always):** `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vupklsh`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vupklsh"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:2038`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L2038)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:129`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L129)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:497`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L497)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4161-4167`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4161-L4167)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vupklsh => {
            let b = crate::vmx::as_i16x8(ctx.vr[instr.rb()]);
            let mut r = [0i32; 4];
            for i in 0..4 { r[i] = b[4 + i] as i32; }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Sign-extend the low 4 of 8 half-words into words.** `VB.h[4..7]` are each reinterpreted as `int16` and sign-extended to `int32` in `VD.w[0..3]`.
- **Inverse of the low half of [`vpkswss`](vpkswss.md)** (within the `int16` range).
- **Big-endian lane ordering.**
- **No saturation, no flags, no VSCR effect.**
- **VMX128 sibling [`vupklsh128`](vupklsh128.md).**

## Related Instructions

- [`vupkhsh`](vupkhsh.md) — high-half half-word unpack.
- [`vupkhsb`](vupkhsb.md), [`vupklsb`](vupklsb.md) — byte → half-word unpacks.
- [`vpkswss`](vpkswss.md), [`vpkswus`](vpkswus.md) — the inverse packs.

## IBM Reference

- [AIX 7.3 — `vupklsh` (Vector Unpack Low Signed Half Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vupklsh-vector-unpack-low-signed-half-word-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)