# `vmsum4fp128` — Vector128 Multiply Sum 4-way Floating-Point

> **Category:** [VMX128](../categories/vmx128.md) · **Form:** [VX128](../forms/VX128.md) · **Opcode:** `0x140001d0`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmsum4fp128` | `vmsum4fp128` | — | Vector128 Multiply Sum 4-way Floating-Point |

## Syntax

```asm
vmsum4fp128 [VD], [VA], [VB]
```

## Encoding

### `vmsum4fp128` — form `VX128`

- **Opcode word:** `0x140001d0`
- **Primary opcode (bits 0–5):** `5`
- **Extended opcode:** `464`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4 or 5) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22 | `—` | reserved |
| 23–25 | `VC` | optional VC / XO sub-field |
| 26 | `VA128h` | source A middle bit |
| 27 | `—` | reserved |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmsum4fp128: read | Source A vector register. |
| `VB` | vmsum4fp128: read | Source B vector register. |
| `VD` | vmsum4fp128: write | Destination vector register. |

## Register Effects

### `vmsum4fp128`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vmsum4fp128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmsum4fp128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1077`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1077)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:106`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L106)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:617`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L617)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4524-4535`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4524-L4535)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vmsum4fp128 => {
            // PPCBUG-436.
            let a = ctx.vr[instr.va128()].as_f32x4();
            let b = ctx.vr[instr.vb128()].as_f32x4();
            let p0 = vmx::flush_denorm(a[0] * b[0]);
            let p1 = vmx::flush_denorm(a[1] * b[1]);
            let p2 = vmx::flush_denorm(a[2] * b[2]);
            let p3 = vmx::flush_denorm(a[3] * b[3]);
            let s = vmx::flush_denorm(p0 + p1 + p2 + p3);
            ctx.vr[instr.vd128()] = xenia_types::Vec128::from_f32x4(s, s, s, s);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **4-way float dot product.** Computes `s = VA[0]*VB[0] + VA[1]*VB[1] + VA[2]*VB[2] + VA[3]*VB[3]` (the full xyzw dot) and **broadcasts `s` to every lane of `VD`**.
- **Scalar-result-splatted-across-lanes.** Direct mirror of HLSL/GLSL's `float4 dot`.
- **Rounding.** Three sequential adds; round-off order affects result by ~1 ulp. Not an FMA in xenia.
- **IEEE-754 binary32; `VSCR[NJ]` honoured.**
- **No VSCR[SAT], no FPSCR update.**
- **VMX128 register-fusion** (7-bit IDs on `VA`, `VB`, `VD`).
- **No IBM AIX entry** — Xenon-only.
- **No `Rc`, no XER.**

## Related Instructions

- [`vmsum3fp128`](vmsum3fp128.md) — 3-way dot-product (ignores the w-lane).
- [`vmulfp128`](vmulfp128.md), [`vaddfp`](../vmx/vaddfp.md) — the building blocks.
- [`vmaddcfp128`](vmaddcfp128.md), [`vmaddfp`](../vmx/vmaddfp.md) — fused MAC variants.
- [`vsumsws`](../vmx/vsumsws.md) — integer sum-reduction analogue.

## IBM Reference

- No IBM AIX entry — Xbox 360 VMX128 extension only.
- Xbox 360 XDK, Altivec-128 (VMX128) extensions. Directly mirrors D3D9's `float4 dot`.
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf) for base float semantics.