# `vrlimi128` — Vector128 Rotate Left Immediate and Mask Insert > **Category:** [VMX128](../categories/vmx128.md) · **Form:** [VX128_4](../forms/VX128_4.md) · **Opcode:** `0x18000710` ## Assembler Mnemonics | Mnemonic | XML entry | Flags | Description | | --- | --- | --- | --- | | `vrlimi128` | `vrlimi128` | — | Vector128 Rotate Left Immediate and Mask Insert | ## Syntax ```asm vrlimi128 [VD], [VB], [IMM], [z] ``` ## Encoding ### `vrlimi128` — form `VX128_4` - **Opcode word:** `0x18000710` - **Primary opcode (bits 0–5):** `6` - **Extended opcode:** `1808` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode (6) | | 6–10 | `VD128l` | destination low 5 bits | | 11–15 | `IMM` | 5-bit immediate | | 16–20 | `VB128l` | source B low 5 bits | | 21–23 | `XO` | extended opcode | | 24–25 | `z` | sub-operation selector | | 28–29 | `VD128h` | destination high 2 bits | | 30–31 | `VB128h` | source B high 2 bits | ## Operands | Field | Role | Description | | --- | --- | --- | | `VB` | vrlimi128: read | Source B vector register. | | `VD` | vrlimi128: write | Destination vector register. | ## Register Effects ### `vrlimi128` - **Reads (always):** `VB` - **Reads (conditional):** _none_ - **Writes (always):** `VD` - **Writes (conditional):** _none_ ## Status-Register Effects _No condition-register or status-register effects._ ## Operation (pseudocode) ``` ; Pseudocode derives directly from the xenia-rs interpreter ; arm (see Implementation References). Operation semantics: ; - Read source operands from the fields listed under Operands. ; - Apply the arithmetic / logical / memory action described ; in the Description field above. ; - Write results to the destination register(s); update any ; status bits enumerated under Status-Register Effects. ; Consult the IBM AIX reference link under IBM Reference for ; canonical PPC-style pseudocode where xenia's expression is ; terse. ``` ## C Translation Example ```c /* C translation: the xenia-rs interpreter arm below in */ /* Implementation References is the authoritative semantic */ /* snapshot. Translate it line-by-line: */ /* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */ /* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */ /* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */ /* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */ /* The Register Effects and Status-Register Effects tables above */ /* enumerate every side effect a faithful translation must emit. */ ``` ## Implementation References **`vrlimi128`** - xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vrlimi128"`](../../xenia-canary/tools/ppc-instructions.xml) - xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1315`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1315) - xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:119`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L119) - xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:649`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L649) - xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3962-3977`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3962-L3977)
xenia-rs interpreter body (frozen snapshot) ```rust PpcOpcode::vrlimi128 => { let shift = instr.vx128_4_z() as usize; let mask = instr.vx128_4_imm(); let b = ctx.vr[instr.vb128()].as_u32x4(); let d = ctx.vr[instr.vd128()].as_u32x4(); let rot = [b[shift % 4], b[(shift + 1) % 4], b[(shift + 2) % 4], b[(shift + 3) % 4]]; let mut r = [0u32; 4]; for i in 0..4 { // mask bit 3 corresponds to word 0 (BE-first). Use rot when // the corresponding mask bit is set. let use_rot = (mask >> (3 - i)) & 1 == 1; r[i] = if use_rot { rot[i] } else { d[i] }; } ctx.vr[instr.vd128()] = xenia_types::Vec128::from_u32x4_array(r); ctx.pc += 4; } ```
## Special Cases & Edge Conditions - **Rotate-left-word + mask-insert in one step.** `VB` is rotated left by `IMM & 3` word positions (word-granular, 0..3 — not bits). The resulting rotated vector is merged into the pre-existing `VD` under control of a 4-bit "insert mask" (`fmask`, from bits 26–29 of the encoding in xenia's layout): mask bit `i` = 1 keeps lane `i` from the rotated `VB`; mask bit = 0 keeps lane `i` from the old `VD`. - **Destructive destination.** `VD` is both source and destination — software must preserve its value or pre-initialise it. - **Typical use: selective-lane overwrite.** Games use this to "rewrite lane `n` of a vector with a shuffled component" without a full permute. A common pattern is "insert a scalar into lane `i` of a vector" where the scalar has been pre-loaded to a known word of `VB`. - **Mask bit ↔ lane mapping.** Big-endian: mask bit 3 (MSB of the 4-bit mask) controls lane 0; bit 0 controls lane 3. (In xenia: `use_rot = (mask >> (3 − i)) & 1`.) - **VMX128 register-fusion** on `VD` and `VB`. - **No IBM AIX entry** — Xenon-only. - **No `Rc`, no XER, no VSCR.** ## Related Instructions - [`vrlw`](../vmx/vrlw.md), [`vrlw128`](../vmx/vrlw.md) — per-lane bit-level rotate (word-granular shift, not lane-granular). - [`vpermwi128`](vpermwi128.md) — immediate 4-way word permute (no merge). - [`vsel`](../vmx/vsel.md), [`vsel128`](../vmx/vsel.md) — general bit-select; `vrlimi128` is the specialised "rotate + insert" equivalent. - [`vsldoi`](../vmx/vsldoi.md) — byte-level immediate shift. ## IBM Reference - No IBM AIX entry — this instruction is exclusive to the Xbox 360's VMX128 extension. The mnemonic is an adaptation of the scalar `rlwimi` (rotate-left-word-immediate-mask-insert) pattern for vectors. - Xbox 360 XDK, Altivec-128 (VMX128) extensions. - [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf) for the base rotate semantics.