# `vupkd3d128` — Vector128 Unpack D3Dtype > **Category:** [VMX128](../categories/vmx128.md) · **Form:** [VX128_3](../forms/VX128_3.md) · **Opcode:** `0x180007f0` ## Assembler Mnemonics | Mnemonic | XML entry | Flags | Description | | --- | --- | --- | --- | | `vupkd3d128` | `vupkd3d128` | — | Vector128 Unpack D3Dtype | ## Syntax ```asm (no disassembly template) ``` ## Encoding ### `vupkd3d128` — form `VX128_3` - **Opcode word:** `0x180007f0` - **Primary opcode (bits 0–5):** `6` - **Extended opcode:** `2032` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode (6) | | 6–10 | `VD128l` | destination low 5 bits | | 11–15 | `IMM` | 5-bit immediate | | 16–20 | `VB128l` | source B low 5 bits | | 21–27 | `XO` | extended opcode | | 28–29 | `VD128h` | destination high 2 bits | | 30–31 | `VB128h` | source B high 2 bits | ## Operands | Field | Role | Description | | --- | --- | --- | | `VB` | vupkd3d128: read | Source B vector register. | | `VD` | vupkd3d128: write | Destination vector register. | ## Register Effects ### `vupkd3d128` - **Reads (always):** `VB` - **Reads (conditional):** _none_ - **Writes (always):** `VD` - **Writes (conditional):** _none_ ## Status-Register Effects _No condition-register or status-register effects._ ## Operation (pseudocode) ``` ; Pseudocode derives directly from the xenia-rs interpreter ; arm (see Implementation References). Operation semantics: ; - Read source operands from the fields listed under Operands. ; - Apply the arithmetic / logical / memory action described ; in the Description field above. ; - Write results to the destination register(s); update any ; status bits enumerated under Status-Register Effects. ; Consult the IBM AIX reference link under IBM Reference for ; canonical PPC-style pseudocode where xenia's expression is ; terse. ``` ## C Translation Example ```c /* C translation: the xenia-rs interpreter arm below in */ /* Implementation References is the authoritative semantic */ /* snapshot. Translate it line-by-line: */ /* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */ /* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */ /* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */ /* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */ /* The Register Effects and Status-Register Effects tables above */ /* enumerate every side effect a faithful translation must emit. */ ``` ## Implementation References **`vupkd3d128`** - xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vupkd3d128"`](../../xenia-canary/tools/ppc-instructions.xml) - xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:2194`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L2194) - xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:128`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L128) - xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:670`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L670) - xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4249-4275`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4249-L4275)
xenia-rs interpreter body (frozen snapshot) ```rust PpcOpcode::vupkd3d128 => { use crate::vmx::D3dPackType; let uimm = crate::decoder::extract_vx128_uimm5(instr.raw); let ty = D3dPackType::from_immediate(uimm >> 2); let src = ctx.vr[instr.vb128()]; let out = match ty { D3dPackType::D3dColor => crate::vmx::unpack_d3dcolor(src), D3dPackType::NormShort2 => crate::vmx::unpack_normshort2(src), D3dPackType::NormPacked32 => crate::vmx::unpack_normpacked32(src), D3dPackType::Float16_2 => crate::vmx::unpack_float16_2(src), D3dPackType::NormShort4 => crate::vmx::unpack_normshort4(src), D3dPackType::Float16_4 => crate::vmx::unpack_float16_4(src), D3dPackType::NormPacked64 => crate::vmx::unpack_normpacked64(src), D3dPackType::Other(t) => { tracing::warn!( raw = format_args!("{:#010x}", instr.raw), uimm, ty = t, "vupkd3d128: unhandled pack type at {:#010x}", ctx.pc, ); src } }; ctx.vr[instr.vd128()] = out; ctx.pc += 4; } ```
## Special Cases & Edge Conditions - **Unpack a D3D-format word into 4 float lanes.** The `IMM` field in the encoding selects the target format: - `D3dColor` — decode a 32-bit RGBA8 (`D3DCOLOR`) into 4 float lanes in `[0.0, 1.0]`. Xenia's helper is `vmx::unpack_d3dcolor`. - Other formats (UBYTE4N, SHORT2N, etc.) are not yet implemented in xenia-rs; the interpreter logs a warning and passes `VB` through unchanged. - **Inverse of [`vpkd3d128`](vpkd3d128.md).** The same format code used to pack must be used to unpack. - **Source-width is a single 32-bit word** of `VB` (typically lane 0; the helpers read the appropriate component). The other three input word lanes are ignored for `D3DCOLOR`. - **IEEE-754 binary32 outputs,** already normalised to `[0.0, 1.0]` (integer value divided by 255, then cast to float). - **No `VSCR[SAT]` effect**, no FPSCR, no exceptions. - **VMX128 register-fusion** on `VD` and `VB`. - **No IBM AIX entry** — Xenon-only. - **No `Rc`, no XER.** ## Related Instructions - [`vpkd3d128`](vpkd3d128.md) — the inverse pack. - [`vupkhpx`](../vmx/vupkhpx.md), [`vupklpx`](../vmx/vupklpx.md) — standard Altivec 1-5-5-5 pixel unpacks. - [`vupkhsb`](../vmx/vupkhsb.md), [`vupklsb`](../vmx/vupklsb.md) — sign-extending byte→half-word unpacks (the integer analogue). - [`vcsxwfp128`](vcsxwfp128.md), [`vcuxwfp128`](vcuxwfp128.md) — int → float with scale; sometimes used as an alternate decode path. ## IBM Reference - No IBM AIX entry — Xbox 360 VMX128 extension only. "D3D" denotes the Direct3D 9 vertex/pixel format catalogue (`D3DDECLTYPE_*`). - Xbox 360 XDK, Altivec-128 (VMX128) extensions. - Microsoft D3D9 documentation: `D3DDECLTYPE_D3DCOLOR`, `D3DDECLTYPE_UBYTE4N`, etc.