xenia-rs/migration/project-root/ppc-manual/alu/addic.md

addic — Add Immediate Carrying

Category: Integer ALU · Form: D · Opcode: 0x30000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
addic	addic	—	Add Immediate Carrying

Syntax

addic [RD], [RA], [SIMM]

Encoding

addic — form D

• Opcode word: 0x30000000
• Primary opcode (bits 0–5): 12
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RA	addic: read	Source GPR (r0–r31).
SIMM	addic: read	16-bit signed immediate. Sign-extended to 64 bits before use.
RD	addic: write	Destination GPR.
CA	addic: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

addic

• Reads (always): RA, SIMM
• Reads (conditional): none
• Writes (always): RD, CA
• Writes (conditional): none

Status-Register Effects

• addic: XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

RT <- (RA) + EXTS(SIMM)
CA <- carry_out

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

addic

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="addic"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:117
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:8
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:336
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:135-144

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::addic => {
            // PPCBUG-002: 32-bit ABI. CA must be from a 32-bit unsigned compare;
            // canary's `AddDidCarry` truncates both operands to int32 first.
            let ra32 = ctx.gpr[instr.ra()] as u32;
            let imm32 = instr.simm16() as i32 as u32;
            let result32 = ra32.wrapping_add(imm32);
            ctx.xer_ca = if result32 < ra32 { 1 } else { 0 };
            ctx.gpr[instr.rd()] = result32 as u64;
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Immediate is sign-extended. SIMM is a 16-bit signed value extended to 64 bits before the add. So addic r3, r4, -1 adds 0xFFFFFFFFFFFFFFFF to r4 — it does not zero-extend.
• XER[CA] always written. Unlike addi, this instruction exists to seed a multi-word add chain with an immediate. Carry-out is computed with the same result < ra unsigned-overflow check as addcx.
• No Rc bit available. This is the non-record form. For a record-form variant that also updates CR0, use addicx (addic.).
• No OE bit either. addic cannot raise / observe signed overflow — only the carry. If you need XER[OV] you must use the XO-form addcx with OE=1.
• RA = 0 reads register r0. Unlike addi, addic does not treat the RA field of zero as a literal zero. The PowerISA gives this instruction the regular RA semantics, not RA0.
• Subtract immediate carrying via negation. There is no subic mnemonic; assemblers synthesise subic RT, RA, value as addic RT, RA, -value (when value fits in 16 bits signed).

Related Instructions

• addicx — same operation plus Rc=1 CR0 update.
• addi — D-form add immediate without XER[CA].
• addis — shifted form (immediate << 16).
• addcx — XO-form: register operands, sets XER[CA].
• subfic — D-form: RT ← SIMM − RA with XER[CA].

IBM Reference

• AIX 7.3 — addic (Add Immediate Carrying)