xenia-rs/migration/project-root/ppc-manual/alu/addzex.md

addzex — Add to Zero Extended

Category: Integer ALU · Form: XO · Opcode: 0x7c000194

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
addze	addzex	—	Add to Zero Extended
addzeo	addzex	OE=1	Add to Zero Extended
addze.	addzex	Rc=1	Add to Zero Extended
addzeo.	addzex	OE=1, Rc=1	Add to Zero Extended

Syntax

addze[OE][Rc] [RD], [RA]

Encoding

addzex — form XO

• Opcode word: 0x7c000194
• Primary opcode (bits 0–5): 31
• Extended opcode: 202
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	addzex: read	Source GPR (r0–r31).
CA	addzex: read; addzex: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.
RD	addzex: write	Destination GPR.
OE	addzex: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	addzex: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

addzex

• Reads (always): RA, CA
• Reads (conditional): none
• Writes (always): RD, CA
• Writes (conditional): OE, CR

Status-Register Effects

• addzex: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

RT <- (RA) + CA
CA <- carry_out

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

addzex

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="addzex"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:172
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:8
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:870
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:223-238

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::addzex => {
            // PPCBUG-015+020: 32-bit truncation.
            let ra32 = ctx.gpr[instr.ra()] as u32;
            let ca = ctx.xer_ca as u32;
            let result32 = ra32.wrapping_add(ca);
            ctx.xer_ca = if result32 < ra32 { 1 } else { 0 };
            ctx.gpr[instr.rd()] = result32 as u64;
            if instr.oe() {
                let true_sum = (ra32 as i32 as i128) + (ca as i128);
                overflow::apply(ctx, true_sum != (result32 as i32) as i128);
            }
            if instr.rc_bit() {
                ctx.update_cr_signed(0, result32 as i32 as i64);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• No RB field used. Like addmex, this XO-form instruction ignores the RB slot. Assemblers emit zero there.
• Operation is RA + 0 + CA ≡ RA + CA. Used to terminate the high word of a multi-word add chain seeded by addcx. After the low-word addc produces the carry, all middle words use addex, and the final word that has no register operand uses addze.
• Carry-out is the simple unsigned overflow test result < ra — same predicate as addcx. CA' = 1 only if RA == ~0 && CA == 1.
• OE=1 not implemented in xenia-rs. The interpreter has no overflow branch at all; spec asks for the standard signed-overflow detect.
• 64-bit CR update on Xenon, 32-bit in xenia-rs (truncation in interpreter.rs:128 — see addx for context).
• Common idiom: extracting a carry as a 0/1. addze rT, 0 (or addze rT, rN where rN == 0) materialises XER[CA] into rT as a plain integer.

Related Instructions

• addmex — terminate with RA + (−1) + CA instead of +0.
• addex — middle of a multi-word add chain.
• addcx — seeds the chain.
• subfzex — subtract dual: ~RA + 0 + CA.

IBM Reference

• AIX 7.3 — addze (Add to Zero Extended)