xenia-rs/migration/project-root/ppc-manual/alu/cmpl.md

cmpl — Compare Logical

Category: Integer ALU · Form: X · Opcode: 0x7c000040

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
cmpl	cmpl	—	Compare Logical

Syntax

cmpl [CRFD], [L], [RA], [RB]

Encoding

cmpl — form X

• Opcode word: 0x7c000040
• Primary opcode (bits 0–5): 31
• Extended opcode: 32
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
L	cmpl: read	Operand-length bit for compare instructions (0 ⇒ 32-bit, 1 ⇒ 64-bit).
RA	cmpl: read	Source GPR (r0–r31).
RB	cmpl: read	Source GPR.
CRFD	cmpl: write	CR destination field (crf, 0–7).

Register Effects

cmpl

• Reads (always): L, RA, RB
• Reads (conditional): none
• Writes (always): CRFD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

if L = 0 then a,b <- (RA)[32:63], (RB)[32:63]
else             a,b <- (RA), (RB)
CR[BF] <- unsigned_compare(a, b) || XER[SO]

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

cmpl

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="cmpl"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:579
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:13
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:761
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:886-894

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::cmpl => {
            let bf = instr.crfd();
            if instr.l() {
                ctx.update_cr_unsigned(bf, ctx.gpr[instr.ra()], ctx.gpr[instr.rb()]);
            } else {
                ctx.update_cr_unsigned(bf, ctx.gpr[instr.ra()] as u32 as u64, ctx.gpr[instr.rb()] as u32 as u64);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Unsigned compare. Treats both operands as unsigned magnitudes. The simplified mnemonics are cmplw (L=0) and cmpld (L=1).
• L = 0: 32-bit operands. Xenia narrows both registers via as u32 as u64 so the high 32 bits of RA/RB are ignored — this matches spec (RA)[32:63] semantics. Most Xbox 360 code uses this mode.
• L = 1: full 64-bit unsigned compare. Used in 64-bit pointer arithmetic; rare in game code but appears in kernel-side helpers.
• SO is copied from XER[SO]. cmpl does not clear or set sticky overflow; it just exposes the current SO in the destination CR field's SO slot.
• BF is a CR field 0–7. Same convention as cmp. Two consecutive cmpl instructions with the same BF simply overwrite the previous result.
• Common signed/unsigned bug. Misusing cmp instead of cmpl (or vice versa) for pointer comparisons is the canonical bug in PPC porting; pointers are always unsigned in C semantics. Always cross-check the comparison polarity in disassembly.
• No Rc/OE and no GPR write — purely a CR-field producer.

Related Instructions

• cmp — signed register compare.
• cmpli — unsigned compare against a 16-bit immediate.
• cmpi — signed immediate compare.
• cmplw, cmpld (simplified) — preferred forms in disassembly.
• mcrxr — clear sticky overflow.

IBM Reference

• AIX 7.3 — cmpl (Compare Logical)
• AIX 7.3 — cmplw / cmpld (simplified mnemonics)