xenia-rs/migration/project-root/ppc-manual/control/mfvscr.md

mfvscr — Move from VSCR

Category: Control / CR / SPR · Form: VX · Opcode: 0x10000604

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mfvscr	mfvscr	—	Move from VSCR

Syntax

(no disassembly template)

Encoding

mfvscr — form VX

• Opcode word: 0x10000604
• Primary opcode (bits 0–5): 4
• Extended opcode: 1540
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VSCR	mfvscr: read	Vector Status and Control Register (NJ/SAT bits).
VD	mfvscr: write	Destination vector register.

Register Effects

mfvscr

• Reads (always): VSCR
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mfvscr

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mfvscr"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:303
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:53
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:539
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2506-2513

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mfvscr => {
            // PPCBUG-080: ISA places VSCR in the rightmost word of VD with
            // bytes 0-11 zeroed. Previously the full 128-bit ctx.vscr was
            // copied (leaking stale upper data to guest).
            let vscr_word = ctx.vscr.as_u32x4()[3];
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array([0, 0, 0, vscr_word]);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Operation. Reads the 32-bit Vector Status and Control Register (VSCR) into the low 32 bits of the rightmost word of VD (the 128-bit vector register). The other 96 bits of VD are zeroed. PowerISA places the result at byte offset 12..15 (big-endian within the 128-bit register).

• VSCR contents (Xenon-relevant).

  Bit	Name	Meaning
  16	NJ	Non-Java mode (denormal handling for IEEE-754 single-prec vector ops)
  31	SAT	Saturation — sticky; set whenever a saturating vector op clamps

  All other bits are reserved (zero).

• SAT is sticky. Once a saturating vector instruction clamps a result, VSCR[SAT] becomes 1 and stays 1 until explicitly cleared via mtvscr. Software polls it after a vector batch to detect overflow.

• NJ controls denormals. When NJ=1 (the Xenon's default), AltiVec single-precision ops flush denormal inputs/outputs to zero (non-IEEE behaviour); NJ=0 enforces full IEEE.

• VRSAVE. Writing the entire 128-bit VD consumes a vector register slot; software wishing to honour VRSAVE bookkeeping should ensure the chosen VD is in the live mask.

• xenia simplification. xenia-rs stores VSCR as a single value of the same vr type (effectively a u128) and copies it directly into ctx.vr[VD]. Saturating ops in xenia-rs do maintain SAT correctly for the vector ops that are implemented; NJ is honoured for the denormal-flush paths but its effect is small in practice.

• Not synchronising.

Related Instructions

• mtvscr — write VSCR from a vector register (the inverse).
• mfspr — for non-vector status registers; VSCR has its own opcode.
• AltiVec saturating-arithmetic ops (e.g., vaddubs, vsubuhs) — primary writers of VSCR[SAT].

mfvscr has no simplified mnemonics.

IBM Reference

• AIX 7.3 — mfvscr (Move from VSCR)
• PowerISA v2.07B, Book I §6.6 — VSCR layout and the SAT / NJ definitions.