xenia-rs/migration/project-root/ppc-manual/control/mtfsfx.md

mtfsfx — Move to FPSCR Fields

Category: Control / CR / SPR · Form: XFL · Opcode: 0xfc00058e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mtfsf	mtfsfx	—	Move to FPSCR Fields
mtfsf.	mtfsfx	Rc=1	Move to FPSCR Fields

Syntax

mtfsf[Rc] [FM], [FB]

Encoding

mtfsfx — form XFL

• Opcode word: 0xfc00058e
• Primary opcode (bits 0–5): 63
• Extended opcode: 711
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (63)
6	L	field-select behaviour
7–14	FM	FPSCR field mask
15	W	immediate-value flag
16–20	FRB	source FPR
21–30	XO	extended opcode
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FM	mtfsfx: read	8-bit FPSCR field-mask used by mtfsf.
FB	mtfsfx: read	Source B floating-point register.
FPSCR	mtfsfx: write	Floating-Point Status and Control Register.
CR	mtfsfx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mtfsfx

• Reads (always): FM, FB
• Reads (conditional): none
• Writes (always): FPSCR
• Writes (conditional): CR

Status-Register Effects

• mtfsfx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtfsfx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mtfsfx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:416
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:55
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:911
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3041-3054

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mtfsfx => {
            // Move to FPSCR fields: fm mask in bits 7-14, frB value
            let fm = (instr.raw >> 17) & 0xFF;
            let val = ctx.fpr[instr.rb()].to_bits() as u32;
            let mut mask = 0u32;
            for i in 0..8 {
                if fm & (1 << (7 - i)) != 0 {
                    mask |= 0xF << (28 - i * 4);
                }
            }
            ctx.fpscr = (ctx.fpscr & !mask) | (val & mask);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• FM is an 8-bit field-mask. Each of the eight bits selects one 4-bit FPSCR field (0..7). FM[0] (0x80) selects FPSCR field 0 (bits 0..3 = FX, FEX, VX, OX), …, FM[7] (0x01) selects FPSCR field 7 (rounding-mode bits RN). Set bits cause that field of FRB's low 32 bits to overwrite the corresponding FPSCR field; clear bits leave the field unchanged.
• Source is the LOW 32 bits of FRB. The high 32 bits are ignored. Software that wants to write a 32-bit pattern typically constructs it in a GPR, stores to memory, and reloads as a double via lfd.
• Most common use: setting rounding mode. Compilers wrap calls to <fenv.h>-style functions with mtfsf 1, fX to update only the rounding-mode field (RN, FPSCR field 7).
• Rc=1 updates CR1. mtfsf. copies FPSCR's top 4 bits (FX, FEX, VX, OX) into CR1 after the write.
• L/W bits. PowerISA v2.05+ adds L=1 to mean "write all FPSCR bits regardless of FM" and W=1 to select the upper or lower 32 bits. xenia-rs ignores L and W (always treats L=0, W=0), which matches every real Xbox 360 use.
• xenia simplification. xenia maintains FPSCR as a u32 and applies the field mask correctly. However, most FP instructions in xenia don't read FPSCR (e.g., divides ignore the rounding mode), so the architecturally-set rounding mode often has no actual effect on results. Acceptable for the title set xenia targets.
• Not synchronising. Reorderable; PowerISA recommends an isync after FPSCR changes that affect subsequent FP behaviour.

Related Instructions

• mtfsfix — write a 4-bit immediate into one FPSCR field (no FPR source needed).
• mtfsb0x, mtfsb1x — single-bit FPSCR write.
• mffsx — read FPSCR into an FPR.
• mcrfs — copy FPSCR field → CR field.

mtfsf is the simplified form (Rc=0); mtfsf. is the recording variant.

IBM Reference

• AIX 7.3 — mtfsf (Move to FPSCR Fields)
• PowerISA v2.07B, Book I §4.6.6 — mtfsf definition and L/W extensions.