xenia-rs/migration/project-root/ppc-manual/control/mtmsrd.md

mtmsrd — Move to Machine State Register Doubleword

Category: Control / CR / SPR · Form: X · Opcode: 0x7c000164 · sync

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mtmsrd	mtmsrd	—	Move to Machine State Register Doubleword

Syntax

mtmsrd [RS]

Encoding

mtmsrd — form X

• Opcode word: 0x7c000164
• Primary opcode (bits 0–5): 31
• Extended opcode: 178
• Synchronising: yes

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	mtmsrd: read	Source GPR (alias for RD in some stores).
MSR	mtmsrd: write	Machine State Register.

Register Effects

mtmsrd

• Reads (always): RS
• Reads (conditional): none
• Writes (always): MSR
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtmsrd

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mtmsrd"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_control.cc:827
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:55
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:785
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1649-1663

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mtmsr | PpcOpcode::mtmsrd => {
            // PPCBUG-078: mtmsrd L=1 is a partial-MSR-write — only MSR[EE]
            // (u64 bit 15) and MSR[RI] (u64 bit 0) are modified; all other
            // MSR bits preserved. Used by kernel code to re-enable external
            // interrupts without disturbing the rest of the MSR.
            let l = (instr.raw >> (31 - 15)) & 1;
            let rs = ctx.gpr[instr.rs()];
            if matches!(instr.opcode, PpcOpcode::mtmsrd) && l == 1 {
                let mask: u64 = (1u64 << 15) | 1u64;
                ctx.msr = (ctx.msr & !mask) | (rs & mask);
            } else {
                ctx.msr = rs;
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Privileged. Like mtmsr, supervisor-only. Game code never emits it.
• 64-bit form. Writes all 64 MSR bits — including MSR[SF] (bit 0) which selects 64-bit mode, MSR[HV] (bit 3, hypervisor), MSR[EE] (32, external interrupts), MSR[PR] (33, problem state), MSR[FP] (34), MSR[ME] (35, machine-check enable), MSR[DR]/MSR[IR] (data/instruction translation, 38/39), MSR[RI] (63, recoverable interrupt). On the Xenon kernel this is the canonical MSR-write instruction.
• L operand. Same L-bit selector as mtmsr: L=1 updates only MSR[EE] and MSR[RI]; L=0 updates the full register. xenia-rs ignores L and always writes the full doubleword (matching the typical kernel use).
• Synchronisation. Marked sync — execution-synchronising. PowerISA recommends isync afterwards if subsequent fetch / data semantics depend on the new MSR.
• xenia model. Shares one interpreter arm with mtmsr: ctx.msr = ctx.gpr[rs]. No architectural side effects beyond writing the storage; no privilege check.
• No CR / XER updates.
• Used in interrupt return paths. Kernel handlers commonly write SRR1 (saved MSR) into MSR via mtmsrd followed by rfid to atomically restore state and jump to SRR0.

Related Instructions

• mfmsr — read MSR.
• mtmsr — 32-bit form (low half only).
• sc — kernel entry; the kernel typically pairs mtmsrd + rfid to return.

mtmsrd has no simplified mnemonics.

IBM Reference

• AIX 7.3 — mtmsrd (Move to Machine State Register Doubleword)
• PowerISA v2.07B, Book III §4.3.1 — MSR field definitions, L-bit semantics, and 64-bit-mode rules.