xenia-rs/migration/project-root/ppc-manual/fpu/fctiwx.md

fctiwx — Floating Convert to Integer Word

Category: Floating-Point · Form: X · Opcode: 0xfc00001c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fctiw	fctiwx	—	Floating Convert to Integer Word
fctiw.	fctiwx	Rc=1	Floating Convert to Integer Word

Syntax

fctiw[Rc] [FD], [FB]

Encoding

fctiwx — form X

• Opcode word: 0xfc00001c
• Primary opcode (bits 0–5): 63
• Extended opcode: 14
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fctiwx: read	Source B floating-point register.
FD	fctiwx: write	Destination floating-point register.
CR	fctiwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fctiwx: write	Floating-Point Status and Control Register.

Register Effects

fctiwx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fctiwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fctiwx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fctiwx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:308
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:27
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:899
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2928-2948

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fctiwx => {
            // Convert to integer word (round per FPSCR[RN]).
            // PPCBUG-230: set XX on inexact.
            let val = ctx.fpr[instr.rb()];
            let result_u32: u32 = if val.is_nan() {
                fpscr::set_exception(ctx, fpscr::VXCVI | if fpscr::is_snan(val) { fpscr::VXSNAN } else { 0 });
                0x8000_0000
            } else if val > (i32::MAX as f64) {
                fpscr::set_exception(ctx, fpscr::VXCVI);
                0x7FFF_FFFF
            } else if val < (i32::MIN as f64) {
                fpscr::set_exception(ctx, fpscr::VXCVI);
                0x8000_0000
            } else {
                if val != val.trunc() { fpscr::set_exception(ctx, fpscr::XX); }
                fpscr::round_to_i32(ctx, val) as u32
            };
            ctx.fpr[instr.rd()] = f64::from_bits(result_u32 as u64);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• binary64 → 32-bit signed integer, current rounding mode. Result is rounded per FPSCR[RN] and packed into the low 32 bits of the destination FPR. The high 32 bits are architecturally undefined per PowerISA but xenia produces zero-extended u32 (i.e. the high 32 bits are 0).
• Explicit saturation in xenia. xenia's body clamps the rounded f64 to [i32::MIN as f64, i32::MAX as f64] before the integer cast — this matches PPC's saturation behaviour for out-of-range positive/negative finite inputs.
• NaN sentinel. xenia returns 0x0000_0000_8000_0000 for NaN inputs (i.e. i32::MIN in the low word). Matches PPC's VXCVI sentinel for NaN/out-of-range.
• Rounding implementation. xenia uses f64::round, which rounds half-cases away from zero rather than to nearest-even. xenia quirk: values like 0.5/1.5/2.5 produce 1/2/3 under xenia vs 0/2/2 on PPC default rounding.
• FPSCR[RN] not honored. xenia always uses f64::round, ignoring the rounding-mode field. xenia quirk for non-default modes.
• FPSCR side effects. PPC: sets XX/FX on inexact, VXCVI on NaN/out-of-range. xenia does not update FPSCR.
• Rc=1 (fctiw.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• Encoding. X-form, primary 63, XO 14. Reads FRB only.
• Common pairing. Followed by stfiwx to store the low-32-bit integer to memory (stfd would write the doubleword including the high bits, which on hardware are undefined).

Related Instructions

• fctiwzx — 32-bit integer with round-toward-zero (truncation).
• fctidx, fctidzx — 64-bit integer variants.
• fcfidx — inverse direction (i64 → f64); for i32 → f64, sign-extend then fcfid.
• stfiwx — store low-32-bits FPR (the canonical companion to fctiw/fctiwz).
• mffsx, mtfsfx — control FPSCR[RN] (currently a no-op under xenia for this instruction).

IBM Reference

• AIX 7.3 — fctiw (Floating Convert to Integer Word)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (high 32 bits are architecturally undefined; only stfiwx is the spec-blessed consumer).