xenia-rs/migration/project-root/ppc-manual/fpu/fmulsx.md

fmulsx — Floating Multiply Single

Category: Floating-Point · Form: A · Opcode: 0xec000032

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fmuls	fmulsx	—	Floating Multiply Single
fmuls.	fmulsx	Rc=1	Floating Multiply Single

Syntax

fmuls[Rc] [FD], [FA], [FC]

Encoding

fmulsx — form A

• Opcode word: 0xec000032
• Primary opcode (bits 0–5): 59
• Extended opcode: 25
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fmulsx: read	Source A floating-point register (fr0–fr31).
FC	fmulsx: read	Source C floating-point register (for madd-style ops).
FD	fmulsx: write	Destination floating-point register.
CR	fmulsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fmulsx: write	Floating-Point Status and Control Register.

Register Effects

fmulsx

• Reads (always): FA, FC
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fmulsx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fmulsx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fmulsx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:97
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:28
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:391
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2606-2615

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fmulsx => {
            let a = ctx.fpr[instr.ra()];
            let c = ctx.fpr[instr.rc()];
            fpscr::check_invalid_mul(ctx, a, c);
            let result = to_single(ctx, a * c);
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, a.is_finite() && c.is_finite());
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• A-form quirk: multiplier is FRC. Operands come from FRA (bits 11–15) and FRC (bits 21–25). xenia decodes via instr.rc() (don't confuse with rc_bit() for the record bit).
• Single precision. Result is rounded to IEEE-754 binary32 then re-encoded into the 64-bit FPR. xenia uses to_single(a * c).
• 0 × ±∞ sets FPSCR[VXIMZ, VX, FX] and yields a quiet NaN.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX and exception bits OX, UX, XX, VXIMZ, VXSNAN. xenia-rs does not maintain FPSCR (xenia quirk).
• Rc=1 (fmuls.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Single-precision overflow returns ±∞ and sets OX/XX/FX.
• Denormal flush. Xenon boots with FPSCR[NI]=1; xenia inherits host IEEE behavior, so subnormal results may differ subtly from hardware.
• Encoding. A-form, primary 59, XO 25.

Related Instructions

• fmulx — double-precision multiply.
• fmaddsx, fmsubsx, fnmaddsx, fnmsubsx — single-precision fused multiply-add family (one rounding step; preferred for dot products).
• faddsx, fsubsx, fdivsx — companion single-precision arithmetic.
• fresx, frsqrtex — reciprocal estimates often paired with fmuls to compute a * (1/b).
• frspx — explicit double→single rounding helper.

IBM Reference

• AIX 7.3 — fmuls (Floating Multiply Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.