xenia-rs/migration/project-root/ppc-manual/fpu/fnabsx.md

fnabsx — Floating Negative Absolute Value

Category: Floating-Point · Form: X · Opcode: 0xfc000110

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fnabs	fnabsx	—	Floating Negative Absolute Value
fnabs.	fnabsx	Rc=1	Floating Negative Absolute Value

Syntax

fnabs[Rc] [FD], [FB]

Encoding

fnabsx — form X

• Opcode word: 0xfc000110
• Primary opcode (bits 0–5): 63
• Extended opcode: 136
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fnabsx: read	Source B floating-point register.
FD	fnabsx: write	Destination floating-point register.
CR	fnabsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

fnabsx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): CR

Status-Register Effects

• fnabsx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

FRT <- set_sign(FRB)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fnabsx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fnabsx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:504
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:29
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:908
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2767-2771

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fnabsx => {
            ctx.fpr[instr.rd()] = -(ctx.fpr[instr.rb()].abs());
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Bit-pattern operation, no rounding. fnabs sets the sign bit (bit 0) of the source binary64 value to 1, producing -|FRB|. No precision change, no exception bits. xenia-rs implements this as -(b.abs()) — the abs clears the sign bit, then negation sets it.
• NaN handling. Returns the source NaN with the sign bit set to 1; payload preserved; signalling/quiet bit unchanged. FPSCR[VXSNAN] is not raised.
• Special values. fnabs(±0) = -0; fnabs(±∞) = -∞; fnabs(±NaN) = -NaN (sign set, payload preserved).
• FPSCR. Hardware does not update FPRF and does not raise any exception bit. Sign-bit ops are not arithmetic.
• Rc=1 (fnabs.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• No FRA. X-form, primary 63, XO 136. Reads FRB only.
• Use case. Less common than fabs/fneg. Useful for unconditional negative-magnitude values, e.g. forcing a value to be on the negative side of zero before a subsequent compare or for bit-pattern setup.

Related Instructions

• fabsx — clear sign bit (positive).
• fnegx — toggle sign bit.
• fmrx — plain register copy.
• fselx — branch-free select; with fabs/fnabs synthesises copysign-like helpers.

IBM Reference

• AIX 7.3 — fnabs (Floating Negative Absolute Value)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.