xenia-rs/migration/project-root/ppc-manual/memory/lswx.md

lswx — Load String Word Indexed

Category: Memory · Form: X · Opcode: 0x7c00042a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lswx	lswx	—	Load String Word Indexed

Syntax

(no disassembly template)

Encoding

lswx — form X

• Opcode word: 0x7c00042a
• Primary opcode (bits 0–5): 31
• Extended opcode: 533
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description

Register Effects

lswx

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lswx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lswx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:732
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:42
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:817
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4644-4662

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lswx => {
            let mut ea = ea_indexed(ctx, instr);
            let nb = ctx.xer() & 0x7F; // XER[25..31]
            let mut rd = instr.rd();
            let mut bytes_left = nb;
            while bytes_left > 0 {
                let mut val = 0u32;
                for byte_idx in 0..4 {
                    if bytes_left == 0 { break; }
                    let b = mem.read_u8(ea) as u32;
                    val |= b << (24 - byte_idx * 8);
                    ea = ea.wrapping_add(1);
                    bytes_left -= 1;
                }
                ctx.gpr[rd] = val as u64;
                rd = (rd + 1) % 32;
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Byte count from XER[25..31]. Unlike lswi (where the count is encoded as RB), lswx reads XER[25..31] for the byte count NB (0..127). Xenia's snapshot does let nb = (ctx.xer() & 0x7F) as u32;. NB = 0 is not the "32 bytes" special case here — zero means literally zero bytes, no registers touched.
• Register packing identical to lswi. Bytes are packed big-endian into successive GPRs starting at RT, four bytes per register, with wraparound r31 → r0. Trailing bytes in the last register are zero-padded on the right.
• RA0 semantics. RA = 0 selects literal zero. The instruction has no update form — RA is not modified.
• Invalid forms. AIX flags as invalid: RT collides with RA or RB within the destination range; XER[25..31] and NB byte stream wraps around through both RA and RB. Xenia performs writes regardless, with last-write-wins semantics.
• Used for non-multiple-of-4 copies. Together with lswi, gives a way to load a runtime-determined byte count without per-byte loops. Compilers don't emit it; rare hand-written copy primitives may.
• Alignment. Architecture allows arbitrary alignment; cache-inhibited storage may raise alignment exceptions on real hardware.
• No FPSCR / CR effects. Pure data movement.

Related Instructions

• lswi — sibling with byte count encoded as RB field (immediate-style).
• stswx, stswi — symmetric stores.
• lmw — word-granular bulk load (no byte tail handling).
• lwz, lbz — scalar loads compilers actually emit.

IBM Reference

• AIX 7.3 — lswx (Load String Word Indexed)
• PowerISA v2.07B Book II § "Load and Store String" for invalid-form rules and XER interaction.