xenia-rs/migration/project-root/ppc-manual/memory/lvehx.md

lvehx — Load Vector Element Half Word Indexed

Category: Memory · Form: X · Opcode: 0x7c00004e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvehx	lvehx	—	Load Vector Element Half Word Indexed

Syntax

lvehx [VD], [RA0], [RB]

Encoding

lvehx — form X

• Opcode word: 0x7c00004e
• Primary opcode (bits 0–5): 31
• Extended opcode: 39
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lvehx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvehx: read	Source GPR.
VD	lvehx: write	Destination vector register.

Register Effects

lvehx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvehx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvehx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:81
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:44
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:763
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1884-1897

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvehx => {
            // Load a halfword from (EA & ~1) into vD at halfword slot
            // (EA & 0xF) >> 1. Other halfword lanes preserved (see lvebx).
            let base = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea_unaligned = base.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            let ea = ea_unaligned & !0x1u32;
            let slot = ((ea_unaligned & 0xF) >> 1) as usize;
            let mut bytes = ctx.vr[instr.rd()].as_bytes();
            let h = mem.read_u16(ea);
            bytes[slot * 2] = (h >> 8) as u8;
            bytes[slot * 2 + 1] = (h & 0xFF) as u8;
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(bytes);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Single half-word element load. Architecturally lvehx loads exactly two bytes from EA (which must be 2-byte aligned) and places them in the half-word lane (EA mod 16) >> 1 of the destination vector; the other 7 half-word lanes are undefined.
• EA must be half-aligned. The low bit of EA is masked by hardware to align to 2 — an odd EA rounds down. Xenia's shared snapshot rounds further, masking to 16-byte alignment.
• Xenia simplification — full-line read. The xenia snapshot is shared with lvebx / lvewx: ea & ~0xF then a full 16-byte read into VD. Architectural undefined lanes are filled in deterministically, which is stronger than hardware guarantees but practically convenient.
• RA0 semantics. When RA = 0, base is literal zero; lvehx VD, 0, RB reads at RB (and, in xenia, the surrounding aligned line).
• No update form. No lvehux exists.
• No VMX128 sibling. No lvehx128 — Xbox 360 code prefers lvx128 plus vperm.
• Big-endian half within the lane. The byte at the lower address is the most-significant byte of the half-word lane.
• Common idiom. Pair with vsplth to broadcast or with vperm to assemble a vector from sparse memory.

Related Instructions

• lvebx, lvewx — byte and word element loads.
• lvx, lvxl — full 16-byte aligned vector loads.
• lvlx, lvrx — load-left / load-right partial-vector ops.
• stvehx — symmetric single-half store.

IBM Reference

• AIX 7.3 — lvehx (Load Vector Element Half Word Indexed)
• PowerISA v2.07B Book I "Vector Facility" § "Vector Load and Store" for lane-placement rules.