xenia-rs/migration/project-root/ppc-manual/memory/lwbrx.md

lwbrx — Load Word Byte-Reverse Indexed

Category: Memory · Form: X · Opcode: 0x7c00042c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lwbrx	lwbrx	—	Load Word Byte-Reverse Indexed

Syntax

lwbrx [RD], [RA0], [RB]

Encoding

lwbrx — form X

• Opcode word: 0x7c00042c
• Primary opcode (bits 0–5): 31
• Extended opcode: 534
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lwbrx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lwbrx: read	Source GPR.
RD	lwbrx: write	Destination GPR.

Register Effects

lwbrx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lwbrx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lwbrx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:641
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:49
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:818
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1799-1805

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lwbrx => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            let val = mem.read_u32(ea);
            ctx.gpr[instr.rd()] = val.swap_bytes() as u64;
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Reads little-endian word. Loads 4 bytes and reverses byte order. With Xenon's big-endian world view, the architectural effect is "load a little-endian word as if it were big-endian" — the standard parser instruction for PNG/ZIP/RIFF/TGA chunk fields, network protocol fields, and PC-side-formatted data.
• Implementation detail. The xenia snapshot calls mem.read_u32(ea).swap_bytes(). read_u32 already returns the host-native value of the big-endian word at EA; swap_bytes then flips it.
• X-form only — no update form. Only the indexed form exists. EA = (RA|0) + RB. Pointer-bumping requires a separate addi.
• RA0 semantics. When RA = 0, base is literal zero; lwbrx RT, 0, RB reads at exact RB.
• Zero-extension to 64 bits. Result occupies the full 64-bit GPR; high 32 bits zero. There is no sign-extending byte-reverse load — combine with extsw if needed.
• Alignment. Hardware tolerates unaligned 4-byte reads. Cache-inhibited storage may raise alignment exceptions on real Xenon.
• Pair with stwbrx. Symmetric byte-reverse store.

Related Instructions

• lhbrx, ldbrx — narrower / wider byte-reverse loads.
• stwbrx — store-word byte-reverse counterpart.
• lwz, lwzx — non-reversing zero-extending word loads.
• lwa, lwax — non-reversing sign-extending word loads.

IBM Reference

• AIX 7.3 — lwbrx (Load Word Byte-Reverse Indexed)
• PowerISA v2.07B Book II § "Byte-Reverse Storage Access".