xenia-rs/migration/project-root/ppc-manual/memory/stvewx.md

stvewx — Store Vector Element Word Indexed

Category: Memory · Form: X · Opcode: 0x7c00018e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvewx	stvewx	—	Store Vector Element Word Indexed
stvewx128	stvewx128	—	Store Vector Element Word Indexed 128

Syntax

stvewx [VS], [RA0], [RB]
stvewx128 [VS], [RA0], [RB]

Encoding

stvewx — form X

• Opcode word: 0x7c00018e
• Primary opcode (bits 0–5): 31
• Extended opcode: 199
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stvewx128 — form VX128_1

• Opcode word: 0x10000183
• Primary opcode (bits 0–5): 4
• Extended opcode: 387
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
VS	stvewx: read; stvewx128: read	Source vector register (alias for VD on stores).
RA0	stvewx: read; stvewx128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvewx: read; stvewx128: read	Source GPR.

Register Effects

stvewx

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stvewx128

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvewx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stvewx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:180
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:77
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:788
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1942-1959

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stvewx => {
            // Store vS[slot] (1 word) at EA & ~3. slot = (EA & 0xF) >> 2.
            let base = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea_unaligned = base.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            let ea = ea_unaligned & !0x3u32;
            // PPCBUG-512: stvewx was missing invalidate_for_write.
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            let slot = ((ea_unaligned & 0xF) >> 2) as usize;
            let bytes = ctx.vr[instr.rs()].as_bytes();
            let w = ((bytes[slot * 4] as u32) << 24)
                  | ((bytes[slot * 4 + 1] as u32) << 16)
                  | ((bytes[slot * 4 + 2] as u32) << 8)
                  | (bytes[slot * 4 + 3] as u32);
            mem.write_u32(ea, w);
            ctx.pc += 4;
        }

stvewx128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stvewx128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:183
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:77
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:416
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3175-3192

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stvewx128 => {
            // Mirror of stvewx: word-align EA, extract one 32-bit lane, write 4 bytes only.
            // Previous code used & !0xF (16-byte) and wrote all 16 bytes, corrupting 12
            // adjacent bytes on every execution (PPCBUG-510).
            let ea_unaligned = ea_indexed(ctx, instr);
            let ea = ea_unaligned & !0x3u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            let slot = ((ea_unaligned & 0xF) >> 2) as usize;
            let bytes = ctx.vr[instr.vs128()].as_bytes();
            let w = ((bytes[slot * 4] as u32) << 24)
                  | ((bytes[slot * 4 + 1] as u32) << 16)
                  | ((bytes[slot * 4 + 2] as u32) << 8)
                  | (bytes[slot * 4 + 3] as u32);
            mem.write_u32(ea, w);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Single word element store. Architecturally stvewx writes exactly four bytes from word lane (EA mod 16) >> 2 of VS to address EA & ~3 (low two bits forced to word-aligned). Other lanes are unaffected, and bytes outside the 4-byte window are unaffected.
• Xenia simplification — full 16-byte write. Both stvewx and stvewx128 snapshots write the full 16 bytes of the source vector at ea & ~0xF. This overwrites 12 bytes that hardware would have left alone.
• EA forced word-aligned. Hardware drops the low two bits; xenia's snapshots drop the low four.
• RA0 semantics. RA = 0 selects literal zero.
• No update form. No stvewux.
• VMX128 sibling (stvewx128). Identical semantics; alternative operand encoding addressing v0..v127 via the split-field 7-bit register index.
• Big-endian word within the lane. The byte at the lower address is the most-significant byte.
• Common idiom. Pair with vspltw to broadcast a 32-bit FP/integer value, then stvewx to commit one lane. Less common than stw from a GPR.

Related Instructions

• stvebx, stvehx — single byte / half element stores.
• stvx, stvx128, stvxl — full 16-byte aligned vector stores.
• stvlx, stvrx — store-left / store-right unaligned ops.
• lvewx, lvewx128 — symmetric single-word loads.

IBM Reference

• AIX 7.3 — stvewx (Store Vector Element Word Indexed)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for stvewx128.