xenia-rs/migration/project-root/ppc-manual/vmx/vlogefp.md

vlogefp — Vector Log2 Estimate Floating Point

Category: VMX (Altivec) · Form: VX · Opcode: 0x100001ca

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vlogefp	vlogefp	—	Vector Log2 Estimate Floating Point
vlogefp128	vlogefp128	—	Vector128 Log2 Estimate Floating Point

Syntax

vlogefp [VD], [VB]
vlogefp128 [VD], [VB]

Encoding

vlogefp — form VX

• Opcode word: 0x100001ca
• Primary opcode (bits 0–5): 4
• Extended opcode: 458
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vlogefp128 — form VX128_3

• Opcode word: 0x180006f0
• Primary opcode (bits 0–5): 6
• Extended opcode: 1776
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vlogefp: read; vlogefp128: read	Source B vector register.
VD	vlogefp: write; vlogefp128: write	Destination vector register.

Register Effects

vlogefp

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vlogefp128

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vlogefp

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vlogefp"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:779
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:99
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:473
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4377-4386

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vlogefp | PpcOpcode::vlogefp128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vlogefp128);
            let (rb, rd) = if is_128 { (instr.vb128(), instr.vd128()) }
                           else { (instr.rb(), instr.rd()) };
            let b = ctx.vr[rb].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = b[i].log2(); }
            ctx.vr[rd] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

vlogefp128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vlogefp128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:782
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:99
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:667
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4377-4386

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vlogefp | PpcOpcode::vlogefp128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vlogefp128);
            let (rb, rd) = if is_128 { (instr.vb128(), instr.vd128()) }
                           else { (instr.rb(), instr.rd()) };
            let b = ctx.vr[rb].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = b[i].log2(); }
            ctx.vr[rd] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Per-lane base-2 logarithm. Each of the four word lanes computes VD[i] = log2(VB[i]) in binary32. Note: the IBM manual specifies a low-precision estimate (≤ 1/32 ULP relative error). Xenia uses Rust's f32::log2, which is full-precision; hardware-precise programs may observe small numerical differences.
• Use vexptefp for the inverse. Pair gives 2^(log2(x)) ≈ x for positive finite x.
• Big-endian word lanes. Lane 0 is the most-significant word.
• NaN, negatives, zero, ±∞. log2(negative) and log2(NaN) produce NaN; log2(+0) = -∞; log2(-0) = -∞ (per IEEE-754); log2(+∞) = +∞. None of these stickies VSCR[SAT] — float ops never touch SAT.
• No exception, no VSCR[SAT] change, no XER change.
• VMX128 sibling (vlogefp128). Identical semantics with the extended encoding.
• Natural log via change-of-base. ln(x) = log2(x) * (1 / log2(e)) — multiply by a constant with vmaddfp.

Related Instructions

• vexptefp — base-2 exponent (the inverse).
• vrefp — reciprocal estimate.
• vrsqrtefp — reciprocal-square-root estimate.
• vmaddfp — fused multiply-add for change-of-base scaling.

IBM Reference

• AIX 7.3 — vlogefp (Vector log2 Estimate Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Estimate Instructions