xenia-rs/migration/project-root/ppc-manual/vmx/vminfp.md

vminfp — Vector Minimum Floating Point

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000044a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vminfp	vminfp	—	Vector Minimum Floating Point
vminfp128	vminfp128	—	Vector128 Minimum Floating Point

Syntax

vminfp [VD], [VA], [VB]
vminfp128 [VD], [VA], [VB]

Encoding

vminfp — form VX

• Opcode word: 0x1000044a
• Primary opcode (bits 0–5): 4
• Extended opcode: 1098
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vminfp128 — form VX128

• Opcode word: 0x180002c0
• Primary opcode (bits 0–5): 6
• Extended opcode: 704
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vminfp: read; vminfp128: read	Source A vector register.
VB	vminfp: read; vminfp128: read	Source B vector register.
VD	vminfp: write; vminfp128: write	Destination vector register.

Register Effects

vminfp

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vminfp128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vminfp

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vminfp"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:899
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:103
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:527
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2137-2144

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vminfp => {
            let a = ctx.vr[instr.ra()].as_f32x4();
            let b = ctx.vr[instr.rb()].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = vmx::min_nan(a[i], b[i]); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

vminfp128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vminfp128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:902
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:103
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:697
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2145-2152

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vminfp128 => {
            let a = ctx.vr[instr.va128()].as_f32x4();
            let b = ctx.vr[instr.vb128()].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = vmx::min_nan(a[i], b[i]); }
            ctx.vr[instr.vd128()] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Per-lane IEEE min. Four word lanes; VD[i] = (VA[i] < VB[i]) ? VA[i] : VB[i].
• NaN propagation surprise. Xenia uses if a < b { a } else { b }, so any NaN comparison evaluates false and the result is VB. The IBM manual specifies NaN-propagating min — i.e. NaN inputs should yield NaN. Hardware's vminfp(NaN, x) = NaN while xenia returns x. Worth checking against vmx.rs for any future correctness fixes.
• Sign of zero. vminfp(+0, -0) returns -0 in xenia (since +0 < -0 is false → returns b = -0); hardware likely returns the negative zero too via the same comparator.
• VSCR[NJ] denormals. With NJ = 1 (Xenon default), denormal inputs are flushed to ±0 before comparison.
• No VSCR[SAT] change, no XER change, no exceptions.
• Big-endian word lanes. Lane 0 is the most-significant word.
• Aliasing legal. vminfp v3, v3, v4 clamps v3 from above by v4.
• VMX128 sibling (vminfp128). Identical comparator semantics with the extended encoding.

Related Instructions

• vmaxfp — the per-lane maximum.
• vcmpgtfp, vcmpgefp — separate compare-and-mask path.
• vsel — combine masks with arbitrary alternatives.
• vmaddfp — fused multiply-add when the min is part of a polynomial.
• vminsw — integer-word min if the lanes are signed integers.

IBM Reference

• AIX 7.3 — vminfp (Vector Minimum Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Min/Max