xenia-rs/migration/project-root/ppc-manual/vmx/vmrghh.md

vmrghh — Vector Merge High Half Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000004c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmrghh	vmrghh	—	Vector Merge High Half Word

Syntax

vmrghh [VD], [VA], [VB]

Encoding

vmrghh — form VX

• Opcode word: 0x1000004c
• Primary opcode (bits 0–5): 4
• Extended opcode: 76
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmrghh: read	Source A vector register.
VB	vmrghh: read	Source B vector register.
VD	vmrghh: write	Destination vector register.

Register Effects

vmrghh

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmrghh

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmrghh"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:968
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:105
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:446
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3998-4005

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmrghh => {
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let mut r = [0u16; 8];
            for i in 0..4 { r[2*i] = a[i]; r[2*i+1] = b[i]; }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Interleave the high (most-significant) four halves of two vectors: VD = {VA[0], VB[0], VA[1], VB[1], VA[2], VB[2], VA[3], VB[3]}.
• Pairs with vmrglh to cover the eight halves of each source. Two-instruction transpose for half-word streams.
• Common usage. Interleave Q15 stereo audio: vmrghh vL_R_high, vLeft, vRight then vmrglh vL_R_low, vLeft, vRight and store to produce the natural L/R/L/R ordering.
• Useful for half-precision colour split. Merge two 4-channel half-precision streams.
• No VSCR interaction, no XER, no exceptions. Pure permute.
• Aliasing legal.
• No VMX128 sibling.

Related Instructions

• vmrglh — the "low half" mirror.
• vmrghb, vmrghw — high-half merge at byte / word width.
• vperm — programmable permute.
• vsldoi — static-offset shift-double.
• vupkhsh — sign-extending unpack of the high half (4 halves → 4 words).

IBM Reference

• AIX 7.3 — vmrghh (Vector Merge High Half Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute / Merge