xenia-rs/migration/project-root/ppc-manual/vmx/vmrglw.md

vmrglw — Vector Merge Low Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000018c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmrglw	vmrglw	—	Vector Merge Low Word
vmrglw128	vmrglw128	—	Vector128 Merge Low Word

Syntax

vmrglw [VD], [VA], [VB]
vmrglw128 [VD], [VA], [VB]

Encoding

vmrglw — form VX

• Opcode word: 0x1000018c
• Primary opcode (bits 0–5): 4
• Extended opcode: 396
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vmrglw128 — form VX128

• Opcode word: 0x18000340
• Primary opcode (bits 0–5): 6
• Extended opcode: 832
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vmrglw: read; vmrglw128: read	Source A vector register.
VB	vmrglw: read; vmrglw128: read	Source B vector register.
VD	vmrglw: write; vmrglw128: write	Destination vector register.

Register Effects

vmrglw

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vmrglw128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmrglw

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmrglw"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1030
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:105
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:470
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2386-2393

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmrglw | PpcOpcode::vmrglw128 => {
            let (va, vb, vd) = vmx_reg_triple(instr);
            let a = ctx.vr[va].as_u32x4();
            let b = ctx.vr[vb].as_u32x4();
            // Merge low words: [a2, b2, a3, b3]
            ctx.vr[vd] = xenia_types::Vec128::from_u32x4(a[2], b[2], a[3], b[3]);
            ctx.pc += 4;
        }

vmrglw128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmrglw128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1033
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:105
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:699
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2386-2393

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmrglw | PpcOpcode::vmrglw128 => {
            let (va, vb, vd) = vmx_reg_triple(instr);
            let a = ctx.vr[va].as_u32x4();
            let b = ctx.vr[vb].as_u32x4();
            // Merge low words: [a2, b2, a3, b3]
            ctx.vr[vd] = xenia_types::Vec128::from_u32x4(a[2], b[2], a[3], b[3]);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Interleave the low (least-significant) two words of two vectors: VD = {VA[2], VB[2], VA[3], VB[3]}. Lane 0 is the most-significant word.
• Pairs with vmrghw to cover the four words of each source. Two-instruction word-level transpose.
• Common usage. Bottom half of a 4×4 packed-float matrix transpose; second-half RGBA pixel re-pack after a vmrghw.
• No VSCR interaction, no XER, no exceptions. Pure permute.
• Aliasing legal.
• VMX128 sibling (vmrglw128). Identical semantics with the extended encoding; xenia routes both via vmx_reg_triple.

Related Instructions

• vmrghw — the "high half" mirror.
• vmrglb, vmrglh — low-half merge at byte / half width.
• vperm, vsldoi — programmable / static permute primitives.
• vspltw — broadcast a single word for blending tasks.

IBM Reference

• AIX 7.3 — vmrglw (Vector Merge Low Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute / Merge