xenia-rs/migration/project-root/ppc-manual/vmx/vpkuhus.md

vpkuhus — Vector Pack Unsigned Half Word Unsigned Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000008e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vpkuhus	vpkuhus	—	Vector Pack Unsigned Half Word Unsigned Saturate
vpkuhus128	vpkuhus128	—	Vector128 Pack Unsigned Half Word Unsigned Saturate

Syntax

vpkuhus [VD], [VA], [VB]
vpkuhus128 [VD], [VA], [VB]

Encoding

vpkuhus — form VX

• Opcode word: 0x1000008e
• Primary opcode (bits 0–5): 4
• Extended opcode: 142
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vpkuhus128 — form VX128

• Opcode word: 0x14000340
• Primary opcode (bits 0–5): 5
• Extended opcode: 832
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vpkuhus: read; vpkuhus128: read	Source A vector register.
VB	vpkuhus: read; vpkuhus128: read	Source B vector register.
VD	vpkuhus: write; vpkuhus128: write	Destination vector register.
VSCR	vpkuhus: write; vpkuhus128: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vpkuhus

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

vpkuhus128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vpkuhus: VSCR[SAT] may be stickied on saturating vector operations.
• vpkuhus128: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vpkuhus

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vpkuhus"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1931
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:115
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:452
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4044-4056

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vpkuhus | PpcOpcode::vpkuhus128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vpkuhus128);
            let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
                               else { (instr.ra(), instr.rb(), instr.rd()) };
            let a = ctx.vr[ra].as_u16x8();
            let b = ctx.vr[rb].as_u16x8();
            let mut r = [0u8; 16]; let mut sat = false;
            for i in 0..8 { let (v, s) = crate::vmx::sat_u16_to_u8(a[i]); r[i] = v; sat |= s; }
            for i in 0..8 { let (v, s) = crate::vmx::sat_u16_to_u8(b[i]); r[8 + i] = v; sat |= s; }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[rd] = xenia_types::Vec128::from_bytes(r);
            ctx.pc += 4;
        }

vpkuhus128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vpkuhus128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1934
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:115
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:628
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4044-4056

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vpkuhus | PpcOpcode::vpkuhus128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vpkuhus128);
            let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
                               else { (instr.ra(), instr.rb(), instr.rd()) };
            let a = ctx.vr[ra].as_u16x8();
            let b = ctx.vr[rb].as_u16x8();
            let mut r = [0u8; 16]; let mut sat = false;
            for i in 0..8 { let (v, s) = crate::vmx::sat_u16_to_u8(a[i]); r[i] = v; sat |= s; }
            for i in 0..8 { let (v, s) = crate::vmx::sat_u16_to_u8(b[i]); r[8 + i] = v; sat |= s; }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[rd] = xenia_types::Vec128::from_bytes(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Unsigned half-word → unsigned byte saturating pack. Each of the 16 input half-word lanes (interpreted as uint16) is clamped to [0, 255]. Values above 255 produce 255 and sticky-set VSCR[SAT].
• Lane-count doubling. 16 half-word lanes → 16 byte lanes; VA first, then VB.
• Pair with vpkuhum when saturation is not desired (truncate the low byte instead).
• VSCR[SAT] is sticky.
• No Rc, no XER.
• VMX128 sibling vpkuhus128.

Related Instructions

• vpkuhum — modulo counterpart.
• vpkshss, vpkshus — signed-input half-word packs.
• vpkuwus, vpkuwum — word → half-word analogues.
• vupkhsb, vupklsb — sign-extending byte → half-word unpacks.
• vperm — programmable alternative for irregular packs.

IBM Reference

• AIX 7.3 — vpkuhus (Vector Pack Unsigned Half Word Unsigned Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting