xenia-rs/migration/project-root/ppc-manual/vmx/vsr.md

vsr — Vector Shift Right

Category: VMX (Altivec) · Form: VX · Opcode: 0x100002c4

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsr	vsr	—	Vector Shift Right

Syntax

vsr [VD], [VA], [VB]

Encoding

vsr — form VX

• Opcode word: 0x100002c4
• Primary opcode (bits 0–5): 4
• Extended opcode: 708
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vsr: read	Source A vector register.
VB	vsr: read	Source B vector register.
VD	vsr: write	Destination vector register.

Register Effects

vsr

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsr

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsr"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1587
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:124
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:495
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3927-3933

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsr => {
            let a = u128::from_be_bytes(ctx.vr[instr.ra()].as_bytes());
            let shift = (ctx.vr[instr.rb()].as_bytes()[15] & 7) as u32;
            let r = if shift == 0 { a } else { a >> shift };
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(r.to_be_bytes());
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Whole-register bit shift-right. The 128-bit value VA is shifted right (toward the LSB end) by N bits, where N = VB.b[15] & 7 — the low 3 bits of the last byte of VB. Bits shifted out the bottom are discarded; zero-fill on the top.
• Shift count constraint. The ISA mandates the same 3-bit count across all of VB; xenia-rs reads only byte 15. Splat the count before use.
• Pair with vsro for up to 127-bit shifts. vsro contributes the byte-granular component; vsr the 0..7 residual bits.
• Big-endian. "Right" means toward the LSB end (VD.b[15]).
• No flags, no VSCR.
• No VMX128 sibling.

Related Instructions

• vsro — whole-register shift-right by octets.
• vsl, vslo — left-shift counterparts.
• vsldoi — static-immediate byte shift of VA ‖ VB.
• vsrb, vsrh, vsrw — per-lane logical shifts.

IBM Reference

• AIX 7.3 — vsr (Vector Shift Right)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate