Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
5.1 KiB
5.1 KiB
vsubcuw — Vector Subtract Carryout Unsigned Word
Category: VMX (Altivec) · Form: VX · Opcode:
0x10000580
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
vsubcuw |
vsubcuw |
— | Vector Subtract Carryout Unsigned Word |
Syntax
vsubcuw [VD], [VA], [VB]
Encoding
vsubcuw — form VX
- Opcode word:
0x10000580 - Primary opcode (bits 0–5):
4 - Extended opcode:
1408 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4) |
| 6–10 | VRT/VD |
destination vector register |
| 11–15 | VRA/VA |
source A vector register |
| 16–20 | VRB/VB |
source B vector register |
| 21–31 | XO |
extended opcode (11 bits) |
Operands
| Field | Role | Description |
|---|---|---|
VA |
vsubcuw: read | Source A vector register. |
VB |
vsubcuw: read | Source B vector register. |
VD |
vsubcuw: write | Destination vector register. |
Register Effects
vsubcuw
- Reads (always):
VA,VB - Reads (conditional): none
- Writes (always):
VD - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
C Translation Example
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
vsubcuw
- xenia-canary XML:
tools/ppc-instructions.xml— search formnem="vsubcuw" - xenia-canary emit:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:1671 - xenia-rs opcode:
crates/xenia-cpu/src/opcode.rs:125 - xenia-rs decoder:
crates/xenia-cpu/src/decoder.rs:536 - xenia-rs interpreter:
crates/xenia-cpu/src/interpreter.rs:3391-3399
xenia-rs interpreter body (frozen snapshot)
PpcOpcode::vsubcuw => {
// "Subtract Carryout": r = 1 if a >= b (no borrow), 0 otherwise.
let a = ctx.vr[instr.ra()].as_u32x4();
let b = ctx.vr[instr.rb()].as_u32x4();
let mut r = [0u32; 4];
for i in 0..4 { r[i] = if a[i] >= b[i] { 1 } else { 0 }; }
ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
ctx.pc += 4;
}
Special Cases & Edge Conditions
- "Borrow out" producer for unsigned word subtract. Each of the 4 lanes produces
1ifVA.w[i] >= VB.w[i](no borrow) and0otherwise. This is an inverted borrow — conventional borrow would be1on underflow, but Altivec'svsubcuwreturns the opposite to match theXER[CA]convention used by scalarsubfc/subfe. - Complements
vadduwm/vaddcuwfor 256-bit (or wider) multi-precision arithmetic. After the lane subtract, chain the 4-bit borrow vector into the next word viavsubeuwm-style helpers (or manual software glue, since Altivec has no directsube). - No saturation, no flags, no VSCR effect. Despite being in the "carry" family,
vsubcuwdoesn't touchVSCR[SAT]. - Big-endian word lanes.
- No VMX128 sibling.
Related Instructions
vsubuwm— the difference value (unsigned modulo).vaddcuw— the paired carry-out producer for unsigned-add.vadduwm— unsigned word add (modulo).