0becc9185a
Data-driven from XENIA_JIT_HIST: after register caching the JIT was 73% native; the frequent uncovered opcodes are VMX128 (the long pole), mtspr/mfspr, update- form loads/stores, and a batch of cheap pure-register integer ops. This does the cheap integer batch (each unblocks any block that only lacked it, and — since a covered block can now chain through where an uncovered op used to break the chain — the gain compounds: more native execution AND longer superblocks). Added to covered() + emit_op, all validated against the interpreter by the diff harness (none are sync_sensitive, so fully covered): - extsbx/extshx/extswx — sign-extend byte/half/word (extsb/extsh write the i32-view zero-extended per the 32-bit ABI, CR0 i32; extsw sign-extends into the full 64, CR0 i64). - cntlzwx/cntlzdx — count leading zeros (Cranelift clz). - negx (OE=0) — rD = 0 - rA (ineg), full 64-bit, CR0 on low 32. - slwx/srwx — word shifts; explicit `sh<32 ? shift : 0` select because the count is rB[58:63] (6 bits) and Cranelift's ishl/ushr mask to 5. - sldx/srdx — doubleword shifts, `sh<64 ? shift : 0` (count 7 bits). New emit_cr0_signed64 for the doubleword-result CR0 (a value with low32==0 but high bits set is eq in the 32-bit view but not the 64-bit one). The carry-setting shifts (sraw*/srad*, set XER-CA) and rotate-double (rldic*) are deferred to later batches. Validated (foreground per the bg-SIGTERM finding): 7/7 jit unit tests; diff MISMATCHES=0 over 47.9M blocks; coverage 75.4% -> 80.6% (single-block, diff mode). Perf (RUST_LOG=warn, -n 3e9 to amortize compiles): chain wall 57952ms -> 54748ms (-5.5% from coverage alone; run_block calls 110M -> 98M = more chaining), chain -14.3% vs interp (63.9s) this session. -n 2e9 understates it (more blocks compiled = more compile cost inside the STEP timer at under-amortized -n). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>