1ffa3fb56d
Pin the 3 hottest guest GPRs (static ra/rb/rd frequency) into callee-saved host regs r12/r13/r14 across a block. RegCache + gld64/gld32/gst64 accessors (dynasm Rq/Rd dynamic regs); ALL 75 GPR-access sites in the emitters routed through the accessors. Prologue loads cached regs / epilogue flushes (both l_cont+l_exit merge); fallback path flushes-before / reloads-after (interpreter touches ctx.gpr; mem/FP helpers don't, and cached regs are callee-saved, so no flush around those). RA=0 literal-0 rule unaffected (emit_ea/load_ra_or_zero never read gpr[0]). Gated by XENIA_JIT_REGCACHE (default off; forced on under cfg(test)); conditional prologue keeps the cache-off codegen unchanged. Golden n200m BYTE-IDENTICAL in all 3 configs (interp / JIT / JIT+RC); 17 differential tests pass with the cache FORCED ON. Measured (min of 6): JIT+RC 4.16s vs JIT 4.14s vs interp 3.80s -> NEUTRAL on this benchmark: per-block setup (5 push/pop + 3 load/flush) + fallback flush/reload (+6 mem ops each) cancels the intra-block savings (blocks ~13 instrs, fallbacks frequent). Correct + default-off; may help more CPU-bound workloads (gameplay, larger hot loops). Definitively: no JIT technique (coverage, deferral, regcache) beats interp on this ~60%-overhead boot/render bench. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>