c36cca14f9
Split the monolithic interpreter into cohesive modules: dedicated decoder (decoder.rs) producing 8-byte DecodedInstr; opcode tables (opcode.rs); explicit traps (trap.rs); FPSCR helpers (fpscr.rs); overflow/carry helpers (overflow.rs); a 4 KiB-page-versioned decode cache and basic-block cache (block_cache.rs); and a full VMX/VMX128 implementation (vmx.rs) covering AltiVec + Xenon's 128-bit extensions. Add the parallel-execution substrate behind --parallel: a 7-party phaser (phaser.rs) for round-based barrier sync, ReservationTable (reservation.rs) for guest LL/SC, and the per-HW-thread scheduler core (scheduler.rs) that owns ThreadRefs, runqueues, and pending IRQs. Disassembler is now the single source of truth: disasm.rs gains the full base + extended + VMX128 mnemonic set, with golden JSON fixtures and a disasm_goldens test suite. Add a criterion-style interpreter bench. context.rs grows the per-thread state the new modules need (reservation slot, FPSCR, vector regs). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
281 lines
10 KiB
Rust
281 lines
10 KiB
Rust
/// All PPC opcodes supported by the Xbox 360, including VMX128 extensions.
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/// Directly mirrors the C++ PPCOpcode enum from ppc_opcode.h.
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#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
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#[repr(u32)]
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#[allow(non_camel_case_types)]
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pub enum PpcOpcode {
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// ALU
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addcx, addex, addi, addic, addicx, addis, addmex, addx, addzex,
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andcx, andisx, andix, andx,
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// Branch
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bcctrx, bclrx, bcx, bx,
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// Compare
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cmp, cmpi, cmpl, cmpli,
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// Count leading zeros
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cntlzdx, cntlzwx,
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// Condition register
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crand, crandc, creqv, crnand, crnor, cror, crorc, crxor,
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// Data cache
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dcbf, dcbi, dcbst, dcbt, dcbtst, dcbz, dcbz128,
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// Division
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divdux, divdx, divwux, divwx,
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// Sync/barrier
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eieio,
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// Logical
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eqvx, extsbx, extshx, extswx,
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// FPU
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fabsx, faddsx, faddx, fcfidx, fcmpo, fcmpu, fctidx, fctidzx, fctiwx, fctiwzx,
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fdivsx, fdivx, fmaddsx, fmaddx, fmrx, fmsubsx, fmsubx, fmulsx, fmulx,
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fnabsx, fnegx, fnmaddsx, fnmaddx, fnmsubsx, fnmsubx, fresx, frspx, frsqrtex,
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fselx, fsqrtsx, fsqrtx, fsubsx, fsubx,
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// Instruction cache
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icbi, isync,
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// Load byte
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lbz, lbzu, lbzux, lbzx,
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// Load doubleword
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ld, ldarx, ldbrx, ldu, ldux, ldx,
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// Load float
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lfd, lfdu, lfdux, lfdx, lfs, lfsu, lfsux, lfsx,
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// Load halfword
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lha, lhau, lhaux, lhax, lhbrx, lhz, lhzu, lhzux, lhzx,
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// Load multiple/string
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lmw, lswi, lswx,
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// Load vector
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lvebx, lvehx, lvewx, lvewx128, lvlx, lvlx128, lvlxl, lvlxl128,
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lvrx, lvrx128, lvrxl, lvrxl128,
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lvsl, lvsl128, lvsr, lvsr128,
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lvx, lvx128, lvxl, lvxl128,
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// Load word
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lwa, lwarx, lwaux, lwax, lwbrx, lwz, lwzu, lwzux, lwzx,
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// Move CR
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mcrf, mcrfs, mcrxr,
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// Move from special
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mfcr, mffsx, mfmsr, mfspr, mftb, mfvscr,
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// Move to special
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mtcrf, mtfsb0x, mtfsb1x, mtfsfix, mtfsfx, mtmsr, mtmsrd, mtspr, mtvscr,
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// Multiply
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mulhdux, mulhdx, mulhwux, mulhwx, mulldx, mulli, mullwx,
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// Logical
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nandx, negx, norx, orcx, ori, oris, orx,
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// Rotate
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rldclx, rldcrx, rldiclx, rldicrx, rldicx, rldimix, rlwimix, rlwinmx, rlwnmx,
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// System call
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sc,
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// Shift
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sldx, slwx, sradix, sradx, srawix, srawx, srdx, srwx,
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// Store byte
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stb, stbu, stbux, stbx,
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// Store doubleword
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std, stdbrx, stdcx, stdu, stdux, stdx,
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// Store float
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stfd, stfdu, stfdux, stfdx, stfiwx, stfs, stfsu, stfsux, stfsx,
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// Store halfword
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sth, sthbrx, sthu, sthux, sthx,
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// Store multiple/string
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stmw, stswi, stswx,
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// Store vector
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stvebx, stvehx, stvewx, stvewx128, stvlx, stvlx128, stvlxl, stvlxl128,
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stvrx, stvrx128, stvrxl, stvrxl128,
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stvx, stvx128, stvxl, stvxl128,
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// Store word
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stw, stwbrx, stwcx, stwu, stwux, stwx,
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// Subtract
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subfcx, subfex, subficx, subfmex, subfx, subfzex,
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// Sync
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sync,
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// Trap
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td, tdi, tw, twi,
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// VMX integer
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vaddcuw, vaddfp, vaddfp128, vaddsbs, vaddshs, vaddsws,
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vaddubm, vaddubs, vadduhm, vadduhs, vadduwm, vadduws,
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vand, vand128, vandc, vandc128,
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vavgsb, vavgsh, vavgsw, vavgub, vavguh, vavguw,
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vcfpsxws128, vcfpuxws128, vcfsx, vcfux,
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vcmpbfp, vcmpbfp128, vcmpeqfp, vcmpeqfp128,
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vcmpequb, vcmpequh, vcmpequw, vcmpequw128,
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vcmpgefp, vcmpgefp128, vcmpgtfp, vcmpgtfp128,
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vcmpgtsb, vcmpgtsh, vcmpgtsw, vcmpgtub, vcmpgtuh, vcmpgtuw,
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vcsxwfp128, vctsxs, vctuxs, vcuxwfp128,
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vexptefp, vexptefp128, vlogefp, vlogefp128,
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vmaddcfp128, vmaddfp, vmaddfp128,
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vmaxfp, vmaxfp128, vmaxsb, vmaxsh, vmaxsw, vmaxub, vmaxuh, vmaxuw,
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vmhaddshs, vmhraddshs,
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vminfp, vminfp128, vminsb, vminsh, vminsw, vminub, vminuh, vminuw,
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vmladduhm,
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vmrghb, vmrghh, vmrghw, vmrghw128, vmrglb, vmrglh, vmrglw, vmrglw128,
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vmsum3fp128, vmsum4fp128,
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vmsummbm, vmsumshm, vmsumshs, vmsumubm, vmsumuhm, vmsumuhs,
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vmulesb, vmulesh, vmuleub, vmuleuh, vmulfp128,
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vmulosb, vmulosh, vmuloub, vmulouh,
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vnmsubfp, vnmsubfp128, vnor, vnor128,
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vor, vor128,
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vperm, vperm128, vpermwi128, vpkd3d128,
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vpkpx, vpkshss, vpkshss128, vpkshus, vpkshus128,
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vpkswss, vpkswss128, vpkswus, vpkswus128,
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vpkuhum, vpkuhum128, vpkuhus, vpkuhus128,
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vpkuwum, vpkuwum128, vpkuwus, vpkuwus128,
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vrefp, vrefp128,
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vrfim, vrfim128, vrfin, vrfin128, vrfip, vrfip128, vrfiz, vrfiz128,
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vrlb, vrlh, vrlimi128, vrlw, vrlw128,
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vrsqrtefp, vrsqrtefp128,
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vsel, vsel128,
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vsl, vslb, vsldoi, vsldoi128, vslh, vslo, vslo128, vslw, vslw128,
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vspltb, vsplth, vspltisb, vspltish, vspltisw, vspltisw128, vspltw, vspltw128,
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vsr, vsrab, vsrah, vsraw, vsraw128, vsrb, vsrh, vsro, vsro128, vsrw, vsrw128,
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vsubcuw, vsubfp, vsubfp128, vsubsbs, vsubshs, vsubsws,
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vsububm, vsububs, vsubuhm, vsubuhs, vsubuwm, vsubuws,
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vsum2sws, vsum4sbs, vsum4shs, vsum4ubs, vsumsws,
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vupkd3d128, vupkhpx, vupkhsb, vupkhsb128, vupkhsh,
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vupklpx, vupklsb, vupklsb128, vupklsh,
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vxor, vxor128,
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// XOR immediate
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xori, xoris, xorx,
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// Invalid
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Invalid,
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}
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impl PpcOpcode {
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/// Returns true if this opcode is a branch instruction.
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pub fn is_branch(&self) -> bool {
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matches!(self, Self::bx | Self::bcx | Self::bclrx | Self::bcctrx)
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}
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/// Returns true if this opcode is a system call.
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pub fn is_syscall(&self) -> bool {
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matches!(self, Self::sc)
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}
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/// Returns true if this opcode unconditionally ends a basic block:
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/// any branch, system call, trap, or `Invalid` (decoder couldn't
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/// recognize the instruction — execution will hit the
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/// `Unimplemented` arm and we don't want to swallow the boundary
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/// inside a cached block).
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///
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/// Notably *not* terminating: `mtmsr`/`mtmsrd`/`isync`/`mfmsr`.
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/// On real hardware these have synchronization semantics (a context
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/// synchronizing event for `isync`, MSR rewrite for the `mt*`s) but
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/// our interpreter has no asynchronous-exception model and no
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/// out-of-order execution — they execute as plain ALU/move ops and
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/// don't change control flow synchronously. Block-cache replay is
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/// still bit-for-bit identical to per-instruction dispatch for
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/// those.
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///
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/// Used by the basic-block cache (`block_cache.rs`) to know when to
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/// stop accumulating instructions during a forward decode walk.
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pub fn terminates_block(&self) -> bool {
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matches!(
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self,
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Self::bx | Self::bcx | Self::bclrx | Self::bcctrx
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| Self::sc
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| Self::td | Self::tdi | Self::tw | Self::twi
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| Self::Invalid
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)
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}
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/// Returns true if this is a load instruction.
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pub fn is_load(&self) -> bool {
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matches!(self,
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Self::lbz | Self::lbzu | Self::lbzux | Self::lbzx |
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Self::lhz | Self::lhzu | Self::lhzux | Self::lhzx |
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Self::lha | Self::lhau | Self::lhaux | Self::lhax |
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Self::lwz | Self::lwzu | Self::lwzux | Self::lwzx |
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Self::lwa | Self::lwax | Self::lwaux |
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Self::ld | Self::ldu | Self::ldux | Self::ldx |
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Self::lfs | Self::lfsu | Self::lfsux | Self::lfsx |
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Self::lfd | Self::lfdu | Self::lfdux | Self::lfdx |
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Self::lhbrx | Self::lwbrx | Self::ldbrx |
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Self::lmw | Self::lswi | Self::lswx |
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Self::lwarx | Self::ldarx
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)
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}
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/// Returns true if this is a store instruction.
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pub fn is_store(&self) -> bool {
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matches!(self,
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Self::stb | Self::stbu | Self::stbux | Self::stbx |
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Self::sth | Self::sthu | Self::sthux | Self::sthx |
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Self::stw | Self::stwu | Self::stwux | Self::stwx |
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Self::std | Self::stdu | Self::stdux | Self::stdx |
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Self::stfs | Self::stfsu | Self::stfsux | Self::stfsx |
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Self::stfd | Self::stfdu | Self::stfdux | Self::stfdx |
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Self::sthbrx | Self::stwbrx | Self::stdbrx |
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Self::stmw | Self::stswi | Self::stswx |
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Self::stwcx | Self::stdcx | Self::stfiwx
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)
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}
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pub fn name(&self) -> &'static str {
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match self {
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Self::Invalid => "invalid",
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_ => {
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// Use debug formatting to get the variant name
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// This is a placeholder - in practice we'd have a lookup table
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"?"
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}
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}
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}
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}
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impl std::fmt::Display for PpcOpcode {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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std::fmt::Debug::fmt(self, f)
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn terminates_block_includes_all_branches() {
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assert!(PpcOpcode::bx.terminates_block());
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assert!(PpcOpcode::bcx.terminates_block());
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assert!(PpcOpcode::bclrx.terminates_block());
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assert!(PpcOpcode::bcctrx.terminates_block());
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}
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#[test]
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fn terminates_block_includes_sc_and_traps() {
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assert!(PpcOpcode::sc.terminates_block());
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assert!(PpcOpcode::td.terminates_block());
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assert!(PpcOpcode::tdi.terminates_block());
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assert!(PpcOpcode::tw.terminates_block());
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assert!(PpcOpcode::twi.terminates_block());
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}
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#[test]
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fn terminates_block_includes_invalid() {
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// Decoder failure must end the block — otherwise an unknown
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// opcode would be replayed inside a cached block without going
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// through the per-instruction Unimplemented path.
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assert!(PpcOpcode::Invalid.terminates_block());
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}
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#[test]
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fn terminates_block_excludes_straight_line_ops() {
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// Common ALU and load/store ops must NOT terminate a block.
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assert!(!PpcOpcode::addi.terminates_block());
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assert!(!PpcOpcode::addis.terminates_block());
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assert!(!PpcOpcode::addx.terminates_block());
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assert!(!PpcOpcode::cmpi.terminates_block());
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assert!(!PpcOpcode::cmp.terminates_block());
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assert!(!PpcOpcode::lwz.terminates_block());
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assert!(!PpcOpcode::stw.terminates_block());
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assert!(!PpcOpcode::lbzx.terminates_block());
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assert!(!PpcOpcode::ori.terminates_block());
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assert!(!PpcOpcode::oris.terminates_block());
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assert!(!PpcOpcode::rlwinmx.terminates_block());
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}
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#[test]
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fn terminates_block_excludes_msr_and_sync_ops() {
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// Documented decision: synchronizing ops execute as ALU within
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// a block since the interpreter has no async-exception model.
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assert!(!PpcOpcode::mtmsr.terminates_block());
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assert!(!PpcOpcode::mtmsrd.terminates_block());
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assert!(!PpcOpcode::isync.terminates_block());
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assert!(!PpcOpcode::sync.terminates_block());
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assert!(!PpcOpcode::mfmsr.terminates_block());
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}
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}
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