506b9554a5
Native lwzx/lhzx/lhax/lbzx/stwx/sthx/stbx (via refactored emit_load_tail/ emit_store_tail + emit_ea_x), slw/srw/sld/srd (variable shifts, non-rc, cmovae zeroes for count>=width), and mfspr/mtspr for the pure LR(8)/CTR(9) registers only (other SPRs have side effects -> fallback). Differential tests indexed_loadstore_matches / shifts_match (sh spanning width boundaries) / spr_lr_ctr_matches. Golden n200m BYTE-IDENTICAL with XENIA_JIT (17 tests green). Measured: fallback execs 13.5M->10.8M (64% below the original 29.7M). BUT throughput ratio only 1.10->1.09 -> DEFINITIVE: on this boot/render benchmark opcode coverage alone can't beat interp. Cutting fallbacks 64% moved the ratio 7 points because the run is ~60% non-CPU-step overhead (Amdahl) AND the remaining fallback is FP-arith (fmadds/fmuls/fadds ~57%), expensive in BOTH paths (small wrapper delta) + FPSCR determinism risk. Below-1.0 needs register caching (attacks native-op cost directly) or a more CPU-bound workload. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>