First real GPU implementation. Ring/PM4 frontend (ring_view,
ring_drain, pm4) drains the command processor; gpu_system owns the
threaded backend (DrainFence RPC + parker/fence helpers from M1) and
the MMIO-mapped register block (mmio_region).
Xenos shader frontend: ucode/{alu,control_flow,fetch,mod}.rs decode
the Xbox 360 microcode, translator.rs lowers it onto the WGSL
xenos_interp interpreter shader (shaders/xenos_interp.wgsl).
shader_metrics.rs counts decode/translate work.
Render state: draw_state, primitive, render_target_cache,
texture_cache, tiled_address (Xenos's swizzled tiled-memory layout),
xenos_constants (register field constants), edram (the 10 MiB EDRAM
model with MSAA), and resolve.rs (TILE_FLUSH copy-out — clear-resolve
plus bitwise-equivalent 32 bpp + 64 bpp paths landed). handle.rs
owns the typed GPU-resource handles the kernel hands out.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
37 lines
1.3 KiB
Rust
37 lines
1.3 KiB
Rust
//! Embedded WGSL shader sources used by the host pipeline.
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/// Xenos uber-shader scaffold (P3). See the comment at the top of
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/// [`XENOS_INTERP_WGSL`] for scope/limits and the plan's P3b target state.
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pub const XENOS_INTERP_WGSL: &str = include_str!("xenos_interp.wgsl");
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#[cfg(test)]
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mod tests {
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use super::*;
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/// Parsing through naga validates the shader against WGSL spec + wgpu's
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/// type system. We don't need a full pipeline to catch typos and layout
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/// mistakes — this test is fast and catches regressions at `cargo test`
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/// time.
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#[test]
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fn xenos_interp_wgsl_parses() {
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let module = naga::front::wgsl::parse_str(XENOS_INTERP_WGSL)
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.expect("xenos_interp.wgsl must parse cleanly");
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// Sanity: we declared two entry points.
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assert!(!module.entry_points.is_empty());
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assert!(
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module
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.entry_points
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.iter()
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.any(|e| e.name == "vs_main" && e.stage == naga::ShaderStage::Vertex),
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"missing vs_main entry"
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);
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assert!(
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module
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.entry_points
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.iter()
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.any(|e| e.name == "fs_main" && e.stage == naga::ShaderStage::Fragment),
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"missing fs_main entry"
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);
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}
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}
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