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MechaCat02 ef93a4fa14 handoff: VSync/event-wedge fixes + iterate 2.A–2.BC research notes

Source changes (dormant parity infra, retained from iterate 2.AI/2.AO):
- xenia-kernel/exports.rs: nt_create_event manual_reset polarity +
  related event wiring
- xenia-gpu/mmio_region.rs: D1MODE_VBLANK_VLINE_STATUS hardcode parity

Also lands the audit-runs/ analysis notes (.md/.txt/.json digests) for the
iterate 2.x VSync/0x10e8/0x1004 wedge investigation. Raw trace dumps
(.jsonl/.gz/.csv/.stdout) and agent worktrees (.claude/) are gitignored as
regenerable local artifacts — see memory + HANDOFF for the running findings.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

2026-06-05 07:19:08 +02:00

4.1 KiB

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Phase C+23 re-validation (2026-05-18)

Protocol followed

Cold-vs-cold per reading-error #31 + #32 + #33 + #34.

✓ Backed up both canary cache locations (xenia-canary/build-cross/bin/Windows/Debug/cache/ and ~/.local/share/Xenia/cache/) to tarballs in xenia-rs/audit-runs/phase-c23-keWait-timeout-encoding/.
✓ Wiped both canary caches + ours's (~/.local/share/xenia-rs/cache/ + /tmp/xrs-cache-c23-*).
✓ Cold-ran ours (50M instructions) against the .iso path — NOT the loose default.xex (per #34).
✓ Cold-ran canary with phase_a_event_log_path set, killed after ~95s timeout, with --mute=true.
✓ Truncated canary log to first 250k events for tid=6 / 20k for sisters (using existing C+19 truncate.py).
✓ Ran diff_events.py with full tid map 6=1,7=2,4=11,12=7,14=9,15=10.
✓ Restored both canary cache backups.
✓ Reverted canary config (phase_a_event_log_path back to "").

Determinism check

3 cold ours runs against .iso, det-fields-only MD5:

run	digest
1	23cf4c4cbf61a577caa4118ab2308ba6
2	23cf4c4cbf61a577caa4118ab2308ba6
3	23cf4c4cbf61a577caa4118ab2308ba6

PASS — bit-stable. Replaces C+22's e1dfcb1559f987b35012a7f2dc6d93f5 baseline (digest moved due to addis behavioral change).

Phase B image hash

image_canonical_sha256 = ea8d160e9369328a5b922258a92113efb8d7 ce3e1a5c12cc521e375985c91c18 — UNCHANGED. The image-loading path is unaffected.

Gate matrix

gate	result
Engine source change minimal	PASS (~25 LOC, 1 file)
CPU tests (xenia-cpu) — pre vs post	288 → 291 (3 new, 0 regressions)
Kernel tests (xenia-kernel)	204 unchanged (no regressions)
Diff-tool source unchanged	PASS
Phase A schema version 1 unchanged	PASS
ours-cold byte-stable across 3 runs	PASS (digest unchanged)
Main matched-prefix preserved at C+22	PASS (104,607)
Sister tid=12→7 advanced	PASS (3 → 4)
Sister tid=4→11 / 7→2 / 14→9 / 15→10	PASS (all preserved)
Phase B image hash preserved	PASS (ea8d160e…)
Canary caches restored	PASS
Canary config restored	PASS
Workspace build clean	PASS
`--mute=true` used	PASS
Renamed binary used (xrs-c23)	PASS
Cold-vs-cold against `.iso`	PASS (per #34)

What changed in the diff-tool report compared to C+22 baseline

metric	C+22	C+23	delta
matched tid=6→1	104,607	104,607	0
matched tid=4→11	11	11	0
matched tid=7→2	32	32	0
matched tid=12→7	3	4	+1
matched tid=14→9	41	41	0
matched tid=15→10	16	16	0
ours-cold total events	121,569	121,569	0
ours-cold det-fields digest	e1dfcb15…	23cf4c4c…	NEW
Phase B image hash	ea8d160e…	ea8d160e…	0

Outcome

C+23 = LANDED. tid=12→7 chain advances +1 (3 → 4).
5 LOC effective engine change (CPU interpreter addis).
3 new regression tests in xenia-cpu (lib tests 288 → 291).
Determinism preserved. Phase B image hash preserved.
All other sister chains and main preserved.
New downstream divergence at idx=4 is C+22-class scheduler determinism (out of scope for this phase).

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