MechaCat02 05f2f72c71 refactor(cpu): vrfin uses stdlib f32::round_ties_even() per reviewer nit ...

P5 review feedback (non-blocking): replace the inline round-to-even
implementation with the stable stdlib intrinsic (Rust 1.77+).
Functionally equivalent; cleaner.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>

2026-05-02 12:37:54 +02:00

..

block_cache.rs

xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches

2026-05-01 16:27:43 +02:00

context.rs

fix(cpu): PPCBUG-151 add reservation_width discriminator to stwcx./stdcx.

2026-05-01 17:44:48 +02:00

decoder.rs

fix(cpu): PPCBUG-700 VMX128 register accessors match canary bitfield layout

2026-05-02 11:22:20 +02:00

disasm.rs

fix(disasm): PPCBUG-641+649 sync/lwsync L-field discrimination

2026-05-02 10:43:24 +02:00

fpscr.rs

fix(cpu): PPCBUG-181/182/183/202/203/205 FMA VXISI + NaN sign preservation

2026-05-02 12:20:02 +02:00

interpreter.rs

refactor(cpu): vrfin uses stdlib f32::round_ties_even() per reviewer nit

2026-05-02 12:37:54 +02:00

lib.rs

xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches

2026-05-01 16:27:43 +02:00

opcode.rs

xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches

2026-05-01 16:27:43 +02:00

overflow.rs

xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches

2026-05-01 16:27:43 +02:00

phaser.rs

xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches

2026-05-01 16:27:43 +02:00

reservation.rs

xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches

2026-05-01 16:27:43 +02:00

scheduler.rs

xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches

2026-05-01 16:27:43 +02:00

trap.rs

xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches

2026-05-01 16:27:43 +02:00

vmx.rs

fix(cpu): PPCBUG-426/427/433 single-FMA vnmsubfp + vctsxs NaN saturation

2026-05-02 12:31:10 +02:00