6bb4355e3d
The publisher splash (title idx0) rendered FLAT in ours while canary samples a texture: ours never decoded the logo's textured pixel shader (E59B2B3D, a `tfetch2D` sprite) even though our guest IM_LOADs the exact same microcode canary does (verified byte-identical against the Wine oracle). The shader was misparsed as flat. Three coupled bugs in the ucode decoder, all off vs canary `gpu/ucode.h`: 1. CF opcode table was off-by-one (`control_flow.rs`): mapped opcode 0→Exec and 1→Exit, but Xenos has 0=kNop, 1=kExec, 2=kExecEnd, 3..6/13..14 the cond-exec variants, 7/8 loop, 9/10 call/return, 11 condjmp, 12 alloc, 15 mark-vs-fetch-done. So a real `kExec` clause was read as a terminal `Exit`, truncating the CF block and dropping every instruction (incl. the `tfetch`) after it. Added Nop/MarkVsFetchDone variants; parse now ends on an END-bit exec clause. 2. exec/loop `address` is an absolute instruction-triple index from shader dword 0, but indexed our post-CF `instructions` slice directly (`ucode/mod.rs`). Rebase addresses by the CF triple count so `address*3` lands on the right instruction. 3. Fetch instruction bitfields were wrong (`ucode/fetch.rs`): `const_index` read from bit 5 (actually `src_reg`) instead of bit 20, and texture `dimension` from dword1 instead of dword2 bit14. The logo's `tfetch ..,tf0` was read as `tf1`, whose empty fetch-constant failed to decode → no texture. Also the `sequence` fetch/ALU bit is bit[0] of each pair, not bit[1] (`shader_metrics.rs`, `translator.rs`, `xenos_interp.wgsl`). Result (--gpu-inline, deterministic 2x): the active PS's `tfetch_slots` now resolves slot 0, the tf0 fetch-constant decodes (fmt K8888), and `gpu.texture.decode` fires (137x at -n 50M; texture_cache_entries 0→1, the only golden field that changed — all draw/swap counts unchanged). The same fixes correct the WGSL uber-shader's fetch/CF walk for the threaded/--ui path. Added a regression test that parses the real E59B2B3D microcode and asserts a tfetch slot is found. Golden re-baselined (texture_cache_entries 0→1). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
436 lines
16 KiB
Rust
436 lines
16 KiB
Rust
//! Host-side static analysis over a [`ParsedShader`], emitted once per unique
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//! shader blob. Produces the observability the plan's P3b/P3c sections call
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//! for (`gpu.shader.interpret{stage,kind}` + `gpu.shader.reject{reason}`), so
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//! the HUD can show when a game is reaching ops the WGSL interpreter falls
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//! back on.
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//!
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//! Analysis is intentionally cheap: it scans each exec clause's instruction
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//! triples, classifies them as ALU / vertex-fetch / texture-fetch using the
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//! owning clause's sequence bitmap, and bumps counters accordingly. No GPU
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//! readback is required — `reject` reasons are inferred from opcode values
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//! alone.
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use metrics::counter;
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use crate::ucode::alu::{decode_alu, sop, vop};
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use crate::ucode::control_flow::ControlFlowInstruction;
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use crate::ucode::fetch::{FetchInstruction, decode_fetch};
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use crate::ucode::ParsedShader;
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/// Walk `parsed` once and emit `gpu.shader.interpret` + `gpu.shader.reject`
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/// counters. `stage` should be `"vs"` or `"ps"`.
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pub fn emit_for(parsed: &ParsedShader, stage: &'static str) {
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let mut alu_count: u64 = 0;
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let mut vfetch_count: u64 = 0;
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let mut tfetch_count: u64 = 0;
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let mut rejects: Vec<(&'static str, u64)> = Vec::new();
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let mut features: Vec<&'static str> = Vec::new();
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for clause in &parsed.cf {
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match clause {
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ControlFlowInstruction::Exec {
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address,
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count,
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sequence,
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..
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} => {
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for i in 0..(*count as usize) {
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let triple_idx = *address as usize + i;
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let base = triple_idx * 3;
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if base + 2 >= parsed.instructions.len() {
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break;
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}
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let words = [
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parsed.instructions[base],
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parsed.instructions[base + 1],
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parsed.instructions[base + 2],
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];
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// sequence: 2 bits per instruction — bit[0]=fetch(1)/ALU(0),
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// bit[1]=serialize (Xenos `ucode.h:226`).
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let is_fetch = ((sequence >> (i * 2)) & 1) != 0;
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if is_fetch {
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match decode_fetch(words) {
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FetchInstruction::Vertex(_) => vfetch_count += 1,
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FetchInstruction::Texture(tf) => {
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tfetch_count += 1;
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match tf.dimension {
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0 => mark_feature(&mut features, "tfetch_1d"),
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2 => mark_feature(&mut features, "tfetch_3d"),
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3 => mark_feature(&mut features, "tfetch_cube"),
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_ => {}
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}
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if tf.dimension != 1 {
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bump(&mut rejects, "texfetch_dimension");
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}
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}
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FetchInstruction::Unknown { .. } => {
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bump(&mut rejects, "fetch_unknown");
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}
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}
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} else {
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alu_count += 1;
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let alu = decode_alu(words);
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if !vec_op_supported(alu.vector_opcode) {
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bump(&mut rejects, "alu_vec_unsupported");
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}
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if !scl_op_supported(alu.scalar_opcode) {
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bump(&mut rejects, "alu_scl_unsupported");
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}
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// Feature-of-interest detection for future phases.
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// Transcendentals + kill + setp + cube/max4 are the
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// high-value signals: they tell us which of the
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// deferred capabilities Sylpheed actually exercises.
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match alu.vector_opcode {
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v if v == vop::CUBE => mark_feature(&mut features, "vec_cube"),
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v if v == vop::MAX4 => mark_feature(&mut features, "vec_max4"),
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v if v == vop::KILL_EQ
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|| v == vop::KILL_GT
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|| v == vop::KILL_GE
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|| v == vop::KILL_NE =>
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{
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mark_feature(&mut features, "vec_kill");
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}
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v if v == vop::CND_EQ
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|| v == vop::CND_GE
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|| v == vop::CND_GT =>
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{
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mark_feature(&mut features, "vec_cnd");
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}
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_ => {}
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}
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match alu.scalar_opcode {
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s if s == sop::EXP
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|| s == sop::LOG
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|| s == sop::LOGC
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|| s == sop::SIN
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|| s == sop::COS =>
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{
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mark_feature(&mut features, "scl_transcendental");
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}
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s if s == sop::RSQ
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|| s == sop::RSQC
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|| s == sop::RSQF
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|| s == sop::SQRT =>
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{
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mark_feature(&mut features, "scl_sqrt_family");
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}
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s if s == sop::SETP_EQ
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|| s == sop::SETP_NE
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|| s == sop::SETP_GT
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|| s == sop::SETP_GE
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|| s == sop::SETP_INV
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|| s == sop::SETP_POP
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|| s == sop::SETP_CLR
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|| s == sop::SETP_RSTR =>
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{
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mark_feature(&mut features, "scl_setp");
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}
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s if s == sop::KILLS_EQ
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|| s == sop::KILLS_GT
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|| s == sop::KILLS_GE
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|| s == sop::KILLS_NE
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|| s == sop::KILLS_ONE =>
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{
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mark_feature(&mut features, "scl_kills");
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}
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_ => {}
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}
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if alu.predicated {
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mark_feature(&mut features, "alu_predicated");
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}
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}
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}
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}
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ControlFlowInstruction::LoopStart { .. }
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| ControlFlowInstruction::LoopEnd { .. } => {
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mark_feature(&mut features, "cf_loop");
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bump(&mut rejects, "cf_loop");
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}
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ControlFlowInstruction::CondJmp { .. } => {
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mark_feature(&mut features, "cf_cond_jmp");
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bump(&mut rejects, "cf_cond_jmp");
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}
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ControlFlowInstruction::CondCall { .. } | ControlFlowInstruction::Return => {
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mark_feature(&mut features, "cf_call_return");
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bump(&mut rejects, "cf_call_return");
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}
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ControlFlowInstruction::Unknown { .. } => {
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bump(&mut rejects, "cf_unknown");
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}
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_ => {}
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}
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}
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counter!("gpu.shader.interpret", "stage" => stage, "kind" => "alu")
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.increment(alu_count);
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counter!("gpu.shader.interpret", "stage" => stage, "kind" => "vfetch")
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.increment(vfetch_count);
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counter!("gpu.shader.interpret", "stage" => stage, "kind" => "tfetch")
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.increment(tfetch_count);
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for (reason, n) in rejects {
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counter!("gpu.shader.reject", "stage" => stage, "reason" => reason).increment(n);
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}
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for name in features {
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counter!("gpu.feature.used", "stage" => stage, "name" => name).increment(1);
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}
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}
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/// Collect the unique texture-fetch-constant slot indices a shader samples.
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///
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/// Walks the same exec-clause / sequence-bitmap path as [`emit_for`] but only
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/// extracts `TextureFetch.fetch_const` slots, deduplicated and in first-seen
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/// order. The GPU draw handler uses this to decide which fetch constants to
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/// decode + cache at draw time (keyed off the *active* pixel shader's real
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/// `tfetch` instructions rather than a hardcoded slot).
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pub fn tfetch_slots(parsed: &ParsedShader) -> Vec<u8> {
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let mut slots: Vec<u8> = Vec::new();
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for clause in &parsed.cf {
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if let ControlFlowInstruction::Exec {
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address,
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count,
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sequence,
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..
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} = clause
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{
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for i in 0..(*count as usize) {
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let base = (*address as usize + i) * 3;
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if base + 2 >= parsed.instructions.len() {
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break;
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}
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// sequence: 2 bits per instruction — bit[0]=fetch(1)/ALU(0),
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// bit[1]=serialize (Xenos `ucode.h:226`).
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let is_fetch = ((sequence >> (i * 2)) & 1) != 0;
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if !is_fetch {
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continue;
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}
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let words = [
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parsed.instructions[base],
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parsed.instructions[base + 1],
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parsed.instructions[base + 2],
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];
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if let FetchInstruction::Texture(tf) = decode_fetch(words) {
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if !slots.contains(&tf.fetch_const) {
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slots.push(tf.fetch_const);
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}
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}
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}
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}
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}
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slots
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}
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fn mark_feature(buf: &mut Vec<&'static str>, name: &'static str) {
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if !buf.contains(&name) {
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buf.push(name);
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}
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}
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fn bump(buf: &mut Vec<(&'static str, u64)>, reason: &'static str) {
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for entry in buf.iter_mut() {
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if entry.0 == reason {
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entry.1 += 1;
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return;
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}
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}
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buf.push((reason, 1));
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}
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fn vec_op_supported(op: u8) -> bool {
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matches!(
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op,
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vop::ADD
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| vop::MUL
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| vop::MAX
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| vop::MIN
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| vop::SEQ
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| vop::SGT
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| vop::SGE
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| vop::SNE
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| vop::FRC
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| vop::TRUNC
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| vop::FLOOR
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| vop::MAD
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| vop::CND_EQ
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| vop::CND_GE
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| vop::CND_GT
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| vop::DOT4
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| vop::DOT3
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| vop::DOT2_ADD
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| vop::MAX4
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| vop::KILL_EQ
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| vop::KILL_GT
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| vop::KILL_GE
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| vop::KILL_NE
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| vop::DST
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)
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}
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fn scl_op_supported(op: u8) -> bool {
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matches!(
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op,
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sop::ADDS
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| sop::ADDS_PREV
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| sop::MULS
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| sop::MULS_PREV
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| sop::MAXS
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| sop::MINS
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| sop::SEQS
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| sop::SGTS
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| sop::SGES
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| sop::SNES
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| sop::FRCS
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| sop::TRUNCS
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| sop::FLOORS
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| sop::EXP
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| sop::LOG
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| sop::LOGC
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| sop::RCP
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| sop::RCPC
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| sop::RCPF
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| sop::RSQ
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| sop::RSQC
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| sop::RSQF
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| sop::SQRT
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| sop::SUBS
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| sop::SUBS_PREV
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| sop::SETP_EQ
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| sop::SETP_NE
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| sop::SETP_GT
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| sop::SETP_GE
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| sop::SETP_INV
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| sop::SETP_POP
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| sop::SETP_CLR
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| sop::SETP_RSTR
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| sop::KILLS_EQ
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| sop::KILLS_GT
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| sop::KILLS_GE
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| sop::KILLS_NE
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| sop::KILLS_ONE
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| sop::SIN
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| sop::COS
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| sop::RETAIN_PREV
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)
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use crate::ucode::alu::{sop, vop};
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use crate::ucode::control_flow::ControlFlowInstruction;
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/// Build a minimal `ParsedShader` with one `Exec` clause containing
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/// `count` ALU triples and assert the `alu` counter path works.
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#[test]
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fn emit_for_runs_on_synthetic_shader() {
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let alu_w2 = (vop::ADD as u32) | ((sop::ADDS as u32) << 6) | (0xF << 12);
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let shader = ParsedShader {
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cf: vec![
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ControlFlowInstruction::Exec {
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address: 0,
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count: 2,
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sequence: 0, // all ALU (no is-fetch bits)
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is_end: false,
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predicated: false,
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predicate_condition: false,
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},
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ControlFlowInstruction::Exit,
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],
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instructions: vec![0, 0, alu_w2, 0, 0, alu_w2],
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};
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// Just smoke: doesn't panic. Counters are validated via metrics
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// exporters elsewhere; we only assert this doesn't throw on a
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// well-formed ParsedShader.
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emit_for(&shader, "vs");
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}
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/// `tfetch_slots` should extract the fetch-constant slot of a texture
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/// fetch (and dedup), and return empty for a flat ALU-only shader.
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#[test]
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fn tfetch_slots_extracts_texture_fetch_constants() {
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// word0: opcode TEXTURE_FETCH (0x01) in low 5 bits, const_index=3 in
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// bits[24:20] (Xenos `ucode.h:844`) → 0x01 | (3 << 20).
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let tfetch_w0: u32 = 0x01 | (3u32 << 20);
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let shader = ParsedShader {
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cf: vec![
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ControlFlowInstruction::Exec {
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address: 0,
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count: 2,
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// instruction 0 is a fetch (bit[0] of its 2-bit field set),
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// instruction 1 is ALU. is_fetch = (sequence >> (i*2)) & 1.
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sequence: 0b00_01,
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is_end: false,
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predicated: false,
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predicate_condition: false,
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},
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ControlFlowInstruction::Exit,
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],
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instructions: vec![tfetch_w0, 0, 0, /* ALU triple */ 0, 0, 0],
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};
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assert_eq!(tfetch_slots(&shader), vec![3]);
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// Flat shader: no fetch bits → no slots.
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let flat = ParsedShader {
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cf: vec![ControlFlowInstruction::Exec {
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address: 0,
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count: 1,
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sequence: 0,
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is_end: false,
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predicated: false,
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predicate_condition: false,
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}],
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instructions: vec![0, 0, 0],
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};
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assert!(tfetch_slots(&flat).is_empty());
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}
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/// P8: a shader containing `LoopStart` should mark `cf_loop` as used
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/// so the HUD can surface which deferred feature a game triggers.
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#[test]
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fn feature_detection_flags_loops_and_kills() {
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let kill_alu_w2 =
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(vop::KILL_EQ as u32) | ((sop::RETAIN_PREV as u32) << 6) | (0xF << 12);
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let shader = ParsedShader {
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cf: vec![
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ControlFlowInstruction::LoopStart {
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address: 0,
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loop_id: 0,
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},
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ControlFlowInstruction::Exec {
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address: 0,
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count: 1,
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sequence: 0,
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is_end: true,
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predicated: false,
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predicate_condition: false,
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},
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],
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instructions: vec![0, 0, kill_alu_w2],
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};
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// Smoke: emits cleanly.
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emit_for(&shader, "ps");
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}
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#[test]
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fn unsupported_ops_classified_as_rejects() {
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// Opcode 63 is outside our supported sets for both pipes.
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let alu_w2 = 63u32 | (63u32 << 6) | (0xF << 12);
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let shader = ParsedShader {
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cf: vec![
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ControlFlowInstruction::Exec {
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address: 0,
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count: 1,
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sequence: 0,
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is_end: true,
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predicated: false,
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predicate_condition: false,
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},
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],
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instructions: vec![0, 0, alu_w2],
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};
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// Again: smoke — but also confirm our static tables reject op 63.
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assert!(!vec_op_supported(63));
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assert!(!scl_op_supported(63));
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emit_for(&shader, "ps");
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}
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}
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