xenia-rs/migration/project-root/ppc-manual/alu/addex.md

addex — Add Extended

Category: Integer ALU · Form: XO · Opcode: 0x7c000114

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
adde	addex	—	Add Extended
addeo	addex	OE=1	Add Extended
adde.	addex	Rc=1	Add Extended
addeo.	addex	OE=1, Rc=1	Add Extended

Syntax

adde[OE][Rc] [RD], [RA], [RB]

Encoding

addex — form XO

• Opcode word: 0x7c000114
• Primary opcode (bits 0–5): 31
• Extended opcode: 138
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	addex: read	Source GPR (r0–r31).
RB	addex: read	Source GPR.
CA	addex: read	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.
RD	addex: write	Destination GPR.
OE	addex: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	addex: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

addex

• Reads (always): RA, RB, CA
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): OE, CR

Status-Register Effects

• addex: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- (RA) + (RB) + CA
CA <- carry_out_of_the_add

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

addex

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="addex"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:83
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:8
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:868
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:206-222

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::addex => {
            // PPCBUG-014+020: 32-bit truncation; CA from u32 unsigned compare.
            let ra32 = ctx.gpr[instr.ra()] as u32;
            let rb32 = ctx.gpr[instr.rb()] as u32;
            let ca = ctx.xer_ca as u32;
            let result32 = ra32.wrapping_add(rb32).wrapping_add(ca);
            ctx.xer_ca = if result32 < ra32 || (ca != 0 && result32 == ra32) { 1 } else { 0 };
            ctx.gpr[instr.rd()] = result32 as u64;
            if instr.oe() {
                let true_sum = (ra32 as i32 as i128) + (rb32 as i32 as i128) + (ca as i128);
                overflow::apply(ctx, true_sum != (result32 as i32) as i128);
            }
            if instr.rc_bit() {
                ctx.update_cr_signed(0, result32 as i32 as i64);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Carry-in is consumed and carry-out is produced. addex is the middle link of a multi-word add chain seeded by addcx: RT ← RA + RB + XER[CA], then XER[CA] ← carry_out.
• Carry-out detection handles both edges. Xenia checks result < ra OR (ca != 0 && result == ra) — that second clause covers the case where adding the carry-in alone causes the result to exactly equal RA (i.e. RB == ~0 && CA == 1), which still constitutes overflow. The naive result < ra test misses it.
• No trap on signed overflow. addeo/addeo. only update XER[OV] and sticky XER[SO]; xenia-rs leaves the OE branch unimplemented.
• 64-bit CR update on Xenon, 32-bit in xenia-rs. The Rc=1 arm uses result as i32 as i64. For multi-word adds whose final word is the high 32 bits of a 64-bit value, this distinction matters; see addx.
• XER[CA] must be initialised by an earlier addcx, subfcx, or mtspr to XER. Reading stale CA from an unrelated instruction is the most common bug in hand-written multi-word arithmetic.
• XER[SO] is sticky until cleared by mcrxr; Rc=1 copies it into CR0[SO].

Related Instructions

• addcx — seeds the carry chain (no CA read, sets CA).
• addmex, addzex — terminate the chain (RA + −1 + CA, RA + 0 + CA).
• addx — plain add without XER[CA].
• subfex — dual: ~RA + RB + XER[CA], used for multi-word subtract.
• addic / addicx — immediate carrying adds that initialise a chain.

IBM Reference

• AIX 7.3 — adde (Add Extended)
• PowerISA v2.07B, Book I, §3.3.8 — defines the RA + RB + CA carry-chain composition.