xenia-rs/migration/project-root/ppc-manual/alu/divdux.md

# `divdux` — Divide Doubleword Unsigned

> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [XO](../forms/XO.md) · **Opcode:** `0x7c000392`

<!-- GENERATED: BEGIN -->

## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `divdu` | `divdux` | — | Divide Doubleword Unsigned |
| `divduo` | `divdux` | OE=1 | Divide Doubleword Unsigned |
| `divdu.` | `divdux` | Rc=1 | Divide Doubleword Unsigned |
| `divduo.` | `divdux` | OE=1, Rc=1 | Divide Doubleword Unsigned |

## Syntax

```asm
divdu[OE][Rc] [RD], [RA], [RB]
```

## Encoding

### `divdux` — form `XO`

- **Opcode word:** `0x7c000392`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `457`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (31) |
| 6–10 | `RT` | destination GPR |
| 11–15 | `RA` | source A |
| 16–20 | `RB` | source B |
| 21 | `OE` | overflow-enable flag |
| 22–30 | `XO` | extended opcode (9 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RA` | divdux: read | Source GPR (`r0`–`r31`). |
| `RB` | divdux: read | Source GPR. |
| `RD` | divdux: write | Destination GPR. |
| `OE` | divdux: write (conditional) | Overflow-enable bit. When 1, the instruction updates `XER[OV]` and stickies `XER[SO]` on signed overflow. |
| `CR` | divdux: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |

## Register Effects

### `divdux`

- **Reads (always):** `RA`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** `OE`, `CR`

## Status-Register Effects

- `divdux`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.; **XER[OV]** ← signed-overflow(result); **XER[SO]** stickies, when `OE=1`.

## Operation (pseudocode)

```
RT <- (RA) /u (RB)                       ; undefined if RB=0
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`divdux`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="divdux"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:217`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L217)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:21`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L21)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:876`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L876)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:480-496`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L480-L496)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::divdux => {
            let ra = ctx.gpr[instr.ra()];
            let rb = ctx.gpr[instr.rb()];
            let ov = overflow::divd_ov_unsigned(rb);
            if ov {
                ctx.gpr[instr.rd()] = 0;
            } else {
                ctx.gpr[instr.rd()] = ra / rb;
            }
            if instr.oe() {
                overflow::apply(ctx, ov);
            }
            if instr.rc_bit() {
                ctx.update_cr_signed(0, ctx.gpr[instr.rd()] as i64);
            }
            ctx.pc += 4;
        }
```
</details>

<!-- GENERATED: END -->

## Special Cases & Edge Conditions

- **Single undefined case.** Division by zero (`RB == 0`). There is no `INT_MIN/−1` overflow because both operands are unsigned. Xenia-rs returns 0 for the divide-by-zero case ([`interpreter.rs:306`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L306)); spec leaves `RT` boundedly undefined.
- **No trap on Xenon.** As with [`divdx`](divdx.md), the processor does not raise an exception; consuming code must guard `RB` first (typically `cmpdi rb, 0; beq skip`).
- **`OE=1` should set `XER[OV]`** on `RB == 0`; xenia-rs ignores `OE` here.
- **`Rc=1` CR0 update is correctly 64-bit.** [`interpreter.rs:311`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L311) uses `as i64` directly, so the CR0 sign comparison reflects the full 64-bit unsigned quotient cast to signed. For very large unsigned quotients (`> INT64_MAX`) this CR0 will report `LT` even though the unsigned interpretation is positive — a rare but real source of CR-misuse bugs.
- **Slow.** Same ~70-cycle non-pipelined cost as the signed variant; consider reciprocal multiply for hot loops.
- **Truncating quotient.** Same C-style toward-zero rounding (trivially equal to floor for unsigned).

## Related Instructions

- [`divdx`](divdx.md) — signed 64-bit divide.
- [`divwux`](divwux.md), [`divwx`](divwx.md) — 32-bit unsigned/signed.
- [`mulldx`](mulldx.md), [`mulhdux`](mulhdux.md) — multiply pair for remainder calculation.
- [`cmpli`](cmpli.md), [`cmpl`](cmpl.md) — guard the divisor.

## IBM Reference

- [AIX 7.3 — `divdu` (Divide Doubleword Unsigned)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-divdu-divide-double-word-unsigned-instruction)