xenia-rs/migration/project-root/ppc-manual/alu/rldcrx.md

rldcrx — Rotate Left Doubleword then Clear Right

Category: Integer ALU · Form: MDS · Opcode: 0x78000012

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldcr	rldcrx	—	Rotate Left Doubleword then Clear Right
rldcr.	rldcrx	Rc=1	Rotate Left Doubleword then Clear Right

Syntax

rldcr[Rc] [RA], [RS], [RB], [ME]

Encoding

rldcrx — form MDS

• Opcode word: 0x78000012
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	RB	source B GPR
21–26	mb/me	6-bit mask field (swapped halves)
27–30	XO	extended opcode
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldcrx: read	Source GPR (alias for RD in some stores).
RB	rldcrx: read	Source GPR.
ME	rldcrx: read	Mask end bit.
RA	rldcrx: write	Source GPR (r0–r31).
CR	rldcrx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldcrx

• Reads (always): RS, RB, ME
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldcrx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldcrx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="rldcrx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:881
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:61
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:734
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:812-821

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::rldcrx => {
            let rs = ctx.gpr[instr.rs()];
            let sh = ctx.gpr[instr.rb()] & 0x3F;
            let me = instr.mb_md();
            let rotated = rs.rotate_left(sh as u32);
            let mask = rld_mask_right(me);
            ctx.gpr[instr.ra()] = rotated & mask;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← ROTL64(RS, RB[58:63]) & MASK(0, ME). Rotate RS left by RB & 0x3F, then clear bits to the right of ME — keep bits 0..ME, force bits ME+1..63 to zero.
• Shift from register. Same as rldclx: only the low 6 bits of RB count.
• ME is a split 6-bit field. Same swap-decoded layout as MB in rldclx: (instr.mb() << 1) | ((raw >> 1) & 1) (interpreter.rs:597). Note that even though it represents ME here, xenia reads it from instr.mb() because the field shares the same encoding slot.
• Mask generation. rld_mask_right(ME) = ~((1 << (63 - ME)) - 1) keeping bits 0..ME. When ME = 63 the mask is all ones; when ME = 0 only bit 0 survives.
• Rc=1 CR0 is correctly 64-bit. Uses as i64 directly (interpreter.rs:602).
• No XER effect.
• Useful for left-shift with arbitrary discard. rldcr RA, RS, RB, 63 - n is functionally close to a left-shift-and-mask sequence, with the rotate variant additionally allowing wrap-around.

Related Instructions

• rldclx — sister: clear left instead of right.
• rldicrx — immediate-shift form.
• rldicx, rldiclx, rldimix — full immediate rotate-and-mask family.
• sldx — plain 64-bit logical left shift (often a strength-reduced equivalent).

IBM Reference

• AIX 7.3 — rldcr (Rotate Left Doubleword then Clear Right)