xenia-rs/migration/project-root/ppc-manual/control/mfmsr.md

mfmsr — Move from Machine State Register

Category: Control / CR / SPR · Form: X · Opcode: 0x7c0000a6 · sync

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mfmsr	mfmsr	—	Move from Machine State Register

Syntax

mfmsr [RD]

Encoding

mfmsr — form X

• Opcode word: 0x7c0000a6
• Primary opcode (bits 0–5): 31
• Extended opcode: 83
• Synchronising: yes

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
MSR	mfmsr: read	Machine State Register.
RD	mfmsr: write	Destination GPR.

Register Effects

mfmsr

• Reads (always): MSR
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mfmsr

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mfmsr"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_control.cc:814
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:53
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:771
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1645-1648

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mfmsr => {
            ctx.gpr[instr.rd()] = ctx.msr;
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Privileged. mfmsr is supervisor-only; executing it from problem state on real hardware raises a Privileged Instruction interrupt. Xbox 360 game code never executes it directly — it appears only in the kernel image (xboxkrnl.exe) and in xenia's HLE bridge.

• MSR layout (Xenon-relevant fields, big-endian bit numbering).

  Bit	Name	Meaning
  32	EE	external interrupts enabled
  33	PR	problem state (1 = user)
  34	FP	floating-point available
  35	ME	machine-check enable
  38	DR	data address translation
  39	IR	instruction address translation
  50	LE	little-endian (always 0 on Xenon)
  63	RI	recoverable interrupt

  The Xenon also exposes MSR[SF] (bit 0) = 1 for 64-bit mode; MSR[HV] (bit 3) for hypervisor. See PowerISA Book III for the full table.

• Synchronisation. Marked sync in xenia's XML — mfmsr is execution-synchronising on real hardware (drains the pipeline before sampling MSR).

• xenia model. xenia-rs stores MSR as a flat u64 and returns it raw. No real bit semantics are modelled — the kernel HLE never observes individual MSR fields. The interpreter ignores privilege.

• Read of an undocumented field returns 0. Most of the MSR is zero in xenia because no path explicitly initialises it.

Related Instructions

• mtmsr — write MSR from a GPR (32-bit form).
• mtmsrd — write the full 64-bit MSR (PPC64 form).
• mfspr — for non-MSR special registers; MSR has its own dedicated opcode.
• sc — kernel entry where MSR transitions occur via rfid/hrfid.

mfmsr has no simplified mnemonics.

IBM Reference

• AIX 7.3 — mfmsr (Move from Machine State Register)
• PowerISA v2.07B, Book III §4.3 — MSR field definitions.