xenia-rs/migration/project-root/ppc-manual/control/mtvscr.md

mtvscr — Move to VSCR

Category: Control / CR / SPR · Form: VX · Opcode: 0x10000644

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mtvscr	mtvscr	—	Move to VSCR

Syntax

(no disassembly template)

Encoding

mtvscr — form VX

• Opcode word: 0x10000644
• Primary opcode (bits 0–5): 4
• Extended opcode: 1604
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VB	mtvscr: read	Source B vector register.
VSCR	mtvscr: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

mtvscr

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VSCR
• Writes (conditional): none

Status-Register Effects

• mtvscr: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtvscr

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mtvscr"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:310
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:55
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:542
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2514-2517

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mtvscr => {
            ctx.vscr = ctx.vr[instr.rb()];
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Operation. Reads the low 32 bits of the rightmost word of VB (bytes 12..15 in big-endian) and stores them into VSCR. Other bits of VB are ignored.
• Bits actually significant. Of the 32 source bits, only NJ (bit 16) and SAT (bit 31) are architecturally meaningful on the Xenon. All other bits should be written as zero; behaviour for non-zero values is implementation-defined.
• Clearing SAT. The dominant use is mtvscr vN with vN zeroed via vxor vN, vN, vN, which writes VSCR=0 and thereby clears the sticky SAT bit before a fresh batch of saturating vector ops.
• Setting NJ. Switching to/from "Java mode" (NJ=0, full IEEE denormal handling) versus "Non-Java mode" (NJ=1, flush-to-zero) is the other meaningful use. Game audio / DSP code occasionally toggles this to match a precise IEEE expectation.
• xenia simplification. xenia-rs stores VSCR identically to a vector register and copies the source straight in: ctx.vscr = ctx.vr[VB]. Subsequent xenia AltiVec ops do consult VSCR[SAT] for sticky updates, so the architecturally-relevant behaviour is preserved. NJ's flush-to-zero semantics are honoured by xenia's vector denormal paths.
• Not synchronising. PowerISA does not require isync after mtvscr, but library code occasionally pairs them as a defensive measure.

Related Instructions

• mfvscr — read VSCR into a vector register (the inverse).
• AltiVec saturating ops (vaddubs, vsubuhs, …) — primary writers of VSCR[SAT]; mtvscr is the only way to clear it.
• mtspr — for non-vector control registers; VSCR has its own opcode.

mtvscr has no simplified mnemonics.

IBM Reference

• AIX 7.3 — mtvscr (Move to VSCR)
• PowerISA v2.07B, Book I §6.6 — VSCR layout, SAT / NJ semantics.