xenia-rs/migration/project-root/ppc-manual/fpu/fnmsubx.md

fnmsubx — Floating Negative Multiply-Subtract

Category: Floating-Point · Form: A · Opcode: 0xfc00003c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fnmsub	fnmsubx	—	Floating Negative Multiply-Subtract
fnmsub.	fnmsubx	Rc=1	Floating Negative Multiply-Subtract

Syntax

fnmsub[Rc] [FD], [FA], [FC], [FB]

Encoding

fnmsubx — form A

• Opcode word: 0xfc00003c
• Primary opcode (bits 0–5): 63
• Extended opcode: 30
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fnmsubx: read	Source A floating-point register (fr0–fr31).
FC	fnmsubx: read	Source C floating-point register (for madd-style ops).
FB	fnmsubx: read	Source B floating-point register.
FD	fnmsubx: write	Destination floating-point register.
CR	fnmsubx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fnmsubx: write	Floating-Point Status and Control Register.

Register Effects

fnmsubx

• Reads (always): FA, FC, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fnmsubx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

FRT <- −((FRA × FRC) − FRB)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fnmsubx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fnmsubx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:232
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:29
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:929
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2721-2734

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fnmsubx => {
            // PPCBUG-203: VXISI. PPCBUG-205: NaN sign preservation.
            let a = ctx.fpr[instr.ra()];
            let c = ctx.fpr[instr.rc()];
            let b = ctx.fpr[instr.rb()];
            fpscr::check_invalid_mul(ctx, a, c);
            fpscr::check_invalid_fma_add(ctx, a, c, b, true);
            let fma = a.mul_add(c, -b);
            let result = if fma.is_nan() { fma } else { -fma };
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, a.is_finite() && b.is_finite() && c.is_finite());
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Single rounding step, then sign flip. Computes −((FRA × FRC) − FRB) = FRB − (FRA × FRC), with one fused rounding. xenia-rs implements this as -(a.mul_add(c, -b)), which is mathematically equivalent.
• NaN sign behaviour. PowerISA: the negation does not flip the sign of a NaN result. xenia uses Rust's Neg which does flip the sign bit on NaNs. Observable only via bit-level inspection. xenia quirk.
• Operand order. Assembler: FD, FA, FC, FB.
• Invalid operations. 0×∞ → VXIMZ; same-signed-infinity collision (e.g. (+∞) − (+∞)) → VXISI. Quiet NaN result.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX, OX, UX, XX, VXIMZ, VXISI, VXSNAN. xenia-rs does not (xenia quirk).
• Rc=1 (fnmsub.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Use case. The canonical Newton-Raphson divide refinement step: x_new = x*(2 - d*x). This is the most common operand pattern in compiled PPC graphics code that does software reciprocals.
• Denormal flush. Xenon boots with FPSCR[NI]=1; xenia uses host IEEE behavior.

Related Instructions

• fnmsubsx — single-precision sibling.
• fmaddx, fmsubx, fnmaddx — other fused multiply-add variants.
• fresx — reciprocal estimate; fnmsub is the workhorse of NR refinement of fres outputs.
• frsqrtex — reciprocal-sqrt estimate; also refined with fnmsub-style chains.
• fmulx, fsubx — non-fused decomposition.

IBM Reference

• AIX 7.3 — fnmsub (Floating Negative Multiply-Subtract)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.